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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! Adding library for File I/O
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-- More information on this site:
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-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
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use std.textio.ALL;
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use ieee.std_logic_textio.all;
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ENTITY testControlUnit IS
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ENTITY testControlUnit IS
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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END testControlUnit;
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END testControlUnit;
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--! @brief ControlUnit Testbench file
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--! @brief ControlUnit Testbench file
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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variable line_out: Line; -- Line that will be written to a file
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file cmdfile: TEXT; -- Define the file 'handle'
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begin
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begin
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-- Reset operation
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-- Reset operation
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REPORT "RESET" SEVERITY NOTE;
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REPORT "RESET" SEVERITY NOTE;
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-- Open source file for write...
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FILE_OPEN(cmdfile,"testCode/testCodeBin.dat",WRITE_MODE);
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reset <= '1';
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reset <= '1';
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wait for 2 ns;
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wait for 2 ns;
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reset <= '0';
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reset <= '0';
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wait for 2 ns;
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wait for 2 ns;
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MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
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MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r0),4) & conv_std_logic_vector(10, 22);
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
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assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
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MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
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MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
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assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
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MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
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MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
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MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
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MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
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MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
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MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22);
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Fetch
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Decode
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wait for CLK_period; -- Execute
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wait for CLK_period; -- Execute
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-- Write the command to a file (This will be usefull for the top Testing later)
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WRITE (line_out, MemoryDataInput);
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WRITELINE (cmdfile, line_out);
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-- Verify if signals for the datapath are valid
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-- Verify if signals for the datapath are valid
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assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
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assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
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assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
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assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
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assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
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assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
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assert outEnDp = disable report "Invalid value" severity FAILURE;
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assert outEnDp = disable report "Invalid value" severity FAILURE;
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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-- Close file
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file_close(cmdfile);
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-- Finish simulation
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-- Finish simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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