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--! @file
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--! @file
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--! @brief Testbench for Alu
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--! @brief Testbench for Datapath
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
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library IEEE;
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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ENTITY testDataPath IS
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ENTITY testDataPath IS
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END testDataPath;
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END testDataPath;
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--! @brief Alu Testbench file
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--! @brief Datapath Testbench file
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--! @details Exercise each Alu operation to verify if the description work as planned
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--! @details Attention to this testbench because it will give you hints on how the control circuit must work....
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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ARCHITECTURE behavior OF testDataPath IS
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ARCHITECTURE behavior OF testDataPath IS
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--! Component declaration to instantiate the Alu circuit
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--! Component declaration to instantiate the Alu circuit
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COMPONENT DataPath
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COMPONENT DataPath
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dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal inputMm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal inputMm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputImm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal inputImm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal outEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
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signal aluOp : std_logic := '0'; --! Wire to connect Test signal to component
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signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
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signal muxSel : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal muxSel : std_logic_vector(2 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal regFileWriteAddr : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileReadAddrA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileReadAddrA : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileReadAddrB : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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BEGIN
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
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uut: DataPath PORT MAP (
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uut: DataPath PORT MAP (
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regFileEnB => regFileEnB,
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regFileEnB => regFileEnB,
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outputDp => outputDp,
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outputDp => outputDp,
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dpFlags => dpFlags
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dpFlags => dpFlags
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);
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- MOV r0,10d ---------------------------------------------------------------------------------
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REPORT "MOV r0,10" SEVERITY NOTE;
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inputImm <= conv_std_logic_vector(10, nBits);
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regFileWriteAddr <= r0;
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aluOp <= alu_pass;
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muxSel <= muxPos(fromImediate);
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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-- Read value in r0 to verify if is equal to 20
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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muxSel <= muxPos(fromRegFileA);
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regFileReadAddrA <= r0; -- Read data from r0 and verify if it's 10
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regFileEnA <= '1';
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outEn <= enable;
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wait for 1 ns; -- Wait for data to settle
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assert outputDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
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wait for 1 ns; -- Finish test case
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muxSel <= (others => 'U');
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regFileEnA <= '0';
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outEn <= disable;
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-- MOV r1,20d ---------------------------------------------------------------------------------
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REPORT "MOV r1,20" SEVERITY NOTE;
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inputImm <= conv_std_logic_vector(20, nBits);
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regFileWriteAddr <= r1;
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aluOp <= alu_pass;
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muxSel <= muxPos(fromImediate);
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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-- Read value in r1 to verify if is equal to 20
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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muxSel <= muxPos(fromRegFileA);
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regFileReadAddrA <= r1; -- Read data from r0 and verify if it's 10
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regFileEnA <= '1';
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outEn <= enable;
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wait for 1 ns; -- Wait for data to settle
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assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
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wait for 1 ns; -- Finish test case
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muxSel <= (others => 'U');
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regFileEnA <= '0';
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outEn <= disable;
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-- MOV r2,r1 (r2 <= r1) --------------------------------------------------------------------
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REPORT "MOV r2,r1" SEVERITY NOTE;
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regFileReadAddrB <= r1; -- Read data from r1
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regFileEnB <= '1';
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regFileWriteAddr <= r2; -- Write data in r2
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muxSel <= muxPos(fromRegFileB); -- Select the PortB output from regFile
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to r1(20)
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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muxSel <= muxPos(fromRegFileA);
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regFileReadAddrA <= r2; -- Read data from r0 and verify if it's 10
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regFileEnA <= '1';
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outEn <= enable;
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wait for 1 ns; -- Wait for data to settle
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assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
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wait for 1 ns; -- Finish test case
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muxSel <= (others => 'U');
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regFileEnA <= '0';
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outEn <= disable;
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-- ADD r2,r0 (r2 <= r2+r0)
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REPORT "ADD r2,r0" SEVERITY NOTE;
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regFileReadAddrA <= r2; -- Read data from r2
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regFileEnA <= '1';
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regFileReadAddrB <= r0; -- Read data from r0
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regFileEnB <= '1';
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aluOp <= alu_sum;
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regFileWriteAddr <= r2; -- Write data in r2
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muxSel <= muxPos(fromAlu); -- Select the Alu output
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to 30(10+20)
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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muxSel <= muxPos(fromRegFileB); -- Must access from other Port otherwise you will need an extra cycle to change it's address
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regFileReadAddrB <= r2; -- Read data from r0 and verify if it's 10
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regFileEnB <= '1';
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outEn <= enable;
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wait for 1 ns; -- Wait for data to settle
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assert outputDp = conv_std_logic_vector(30, nBits) report "Invalid value" severity FAILURE;
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wait for 1 ns; -- Finish test case
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muxSel <= (others => 'U');
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regFileEnA <= '0';
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outEn <= disable;
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-- insert stimulus here
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-- Finish simulation
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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