| Line 134... |
Line 134... |
wait for 1 ns; -- Finish test case
|
wait for 1 ns; -- Finish test case
|
muxSel <= (others => 'U');
|
muxSel <= (others => 'U');
|
regFileEnA <= '0';
|
regFileEnA <= '0';
|
outEn <= disable;
|
outEn <= disable;
|
|
|
|
|
-- MOV r2,r1 (r2 <= r1) --------------------------------------------------------------------
|
-- MOV r2,r1 (r2 <= r1) --------------------------------------------------------------------
|
REPORT "MOV r2,r1" SEVERITY NOTE;
|
REPORT "MOV r2,r1" SEVERITY NOTE;
|
regFileReadAddrB <= r1; -- Read data from r1
|
regFileReadAddrB <= r1; -- Read data from r1
|
regFileEnB <= '1';
|
regFileEnB <= '1';
|
regFileWriteAddr <= r2; -- Write data in r2
|
regFileWriteAddr <= r2; -- Write data in r2
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| Line 155... |
Line 156... |
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
|
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
|
wait for 1 ns; -- Finish test case
|
wait for 1 ns; -- Finish test case
|
muxSel <= (others => 'U');
|
muxSel <= (others => 'U');
|
regFileEnA <= '0';
|
regFileEnA <= '0';
|
outEn <= disable;
|
outEn <= disable;
|
|
wait for 1 ns; -- Finish test case
|
|
|
-- ADD r2,r0 (r2 <= r2+r0)
|
-- ADD r2,r0 (r2 <= r2+r0)
|
REPORT "ADD r2,r0" SEVERITY NOTE;
|
REPORT "ADD r2,r0" SEVERITY NOTE;
|
regFileReadAddrA <= r2; -- Read data from r2
|
regFileReadAddrA <= r2; -- Read data from r2
|
regFileEnA <= '1';
|
regFileEnA <= '1';
|
| Line 179... |
Line 181... |
wait for 1 ns; -- Wait for data to settle
|
wait for 1 ns; -- Wait for data to settle
|
assert outputDp = conv_std_logic_vector(30, nBits) report "Invalid value" severity FAILURE;
|
assert outputDp = conv_std_logic_vector(30, nBits) report "Invalid value" severity FAILURE;
|
wait for 1 ns; -- Finish test case
|
wait for 1 ns; -- Finish test case
|
muxSel <= (others => 'U');
|
muxSel <= (others => 'U');
|
regFileEnA <= '0';
|
regFileEnA <= '0';
|
|
regFileEnB <= '0';
|
|
outEn <= disable;
|
|
wait for 1 ns; -- If you don't use this wait the signals will not change...! (Take care of this when implementing the ControlUnit)
|
|
|
|
-- ADD r3,r2,r0 (r3 <= r2+r0)
|
|
REPORT "ADD r3,r2,r0" SEVERITY NOTE;
|
|
regFileReadAddrA <= r2; -- Read data from r2
|
|
regFileEnA <= '1';
|
|
regFileReadAddrB <= r0; -- Read data from r0
|
|
regFileEnB <= '1';
|
|
aluOp <= alu_sum;
|
|
regFileWriteAddr <= r3; -- Write data in r2
|
|
muxSel <= muxPos(fromAlu); -- Select the Alu output
|
|
regFileWriteEn <= '1';
|
|
wait for CLK_period; -- Wait for clock cycle to write into r2
|
|
-- Read value in r2 to verify if is equal to 30(10+20)
|
|
regFileWriteEn <= '0';
|
|
inputImm <= (others => 'U');
|
|
muxSel <= muxPos(fromRegFileB); -- Must access from other Port otherwise you will need an extra cycle to change it's address
|
|
regFileReadAddrB <= r3; -- Read data from r0 and verify if it's 10
|
|
regFileEnB <= '1';
|
|
outEn <= enable;
|
|
wait for 1 ns; -- Wait for data to settle
|
|
assert outputDp = conv_std_logic_vector(40, nBits) report "Invalid value" severity FAILURE;
|
|
wait for 1 ns; -- Finish test case
|
|
muxSel <= (others => 'U');
|
|
regFileEnA <= '0';
|
|
regFileEnB <= '0';
|
outEn <= disable;
|
outEn <= disable;
|
|
|
|
|
-- Finish simulation
|
-- Finish simulation
|
assert false report "NONE. End of simulation." severity failure;
|
assert false report "NONE. End of simulation." severity failure;
|
