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Line 9... |
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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ENTITY testDataPath IS
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ENTITY testDataPath IS
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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END testDataPath;
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END testDataPath;
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--! @brief Datapath Testbench file
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--! @brief Datapath Testbench file
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--! @details Attention to this testbench because it will give you hints on how the control circuit must work....
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--! @details Attention to this testbench because it will give you hints on how the control circuit must work....
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal inputMm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputMm : std_logic_vector(n downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputImm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputImm : std_logic_vector(n downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
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signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
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signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
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signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
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signal muxSel : std_logic_vector(2 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal muxSel : std_logic_vector(2 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal muxRegFile : std_logic_vector(1 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal muxRegFile : std_logic_vector(1 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
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signal outputDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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signal dpFlags : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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constant CLK_period : time := 10 ns;
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