| Line 26... |
Line 26... |
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
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clk : in STD_LOGIC; --! Clock signal
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clk : in STD_LOGIC; --! Clock signal
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outEn : in typeEnDis; --! Enable/Disable datapath output
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outEn : in typeEnDis; --! Enable/Disable datapath output
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aluOp : in aluOps; --! Alu operations
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aluOp : in aluOps; --! Alu operations
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
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muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
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muxRegFile : in dpMuxAluIn; --! Select Alu InputA (Memory,Imediate,RegFileA)
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteAddr : in generalRegisters; --! General register write address
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
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| Line 45... |
Line 45... |
signal inputImm : std_logic_vector(n downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal inputImm : std_logic_vector(n downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
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signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
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signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
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signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
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signal muxSel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
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signal muxSel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
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signal muxRegFile : std_logic_vector(1 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
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signal muxRegFile : dpMuxAluIn := fromMemory; --! Wire to connect Test signal to component
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signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileReadAddrA : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileReadAddrA : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
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| Line 99... |
Line 99... |
REPORT "MOV r0,10" SEVERITY NOTE;
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REPORT "MOV r0,10" SEVERITY NOTE;
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inputImm <= conv_std_logic_vector(10, nBits);
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inputImm <= conv_std_logic_vector(10, nBits);
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regFileWriteAddr <= r0;
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regFileWriteAddr <= r0;
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aluOp <= alu_pass;
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aluOp <= alu_pass;
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muxSel <= fromImediate;
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muxSel <= fromImediate;
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muxRegFile <= muxRegPos(fromRegFileA);
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muxRegFile <= fromRegFileA;
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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-- Read value in r0 to verify if is equal to 20
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-- Read value in r0 to verify if is equal to 20
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regFileWriteEn <= '0';
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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inputImm <= (others => 'U');
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| Line 123... |
Line 123... |
REPORT "MOV r1,20" SEVERITY NOTE;
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REPORT "MOV r1,20" SEVERITY NOTE;
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inputImm <= conv_std_logic_vector(20, nBits);
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inputImm <= conv_std_logic_vector(20, nBits);
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regFileWriteAddr <= r1;
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regFileWriteAddr <= r1;
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aluOp <= alu_pass;
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aluOp <= alu_pass;
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muxSel <= fromImediate;
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muxSel <= fromImediate;
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muxRegFile <= muxRegPos(fromRegFileA);
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muxRegFile <= fromRegFileA;
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
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-- Read value in r1 to verify if is equal to 20
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-- Read value in r1 to verify if is equal to 20
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regFileWriteEn <= '0';
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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inputImm <= (others => 'U');
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Line 147... |
REPORT "MOV r2,r1" SEVERITY NOTE;
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REPORT "MOV r2,r1" SEVERITY NOTE;
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regFileReadAddrB <= r1; -- Read data from r1
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regFileReadAddrB <= r1; -- Read data from r1
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regFileEnB <= '1';
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regFileEnB <= '1';
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regFileWriteAddr <= r2; -- Write data in r2
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regFileWriteAddr <= r2; -- Write data in r2
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muxSel <= fromRegFileB; -- Select the PortB output from regFile
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muxSel <= fromRegFileB; -- Select the PortB output from regFile
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muxRegFile <= muxRegPos(fromRegFileA);
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muxRegFile <= fromRegFileA;
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to r1(20)
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-- Read value in r2 to verify if is equal to r1(20)
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regFileWriteEn <= '0';
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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inputImm <= (others => 'U');
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| Line 174... |
Line 174... |
regFileReadAddrB <= r0; -- Read data from r0
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regFileReadAddrB <= r0; -- Read data from r0
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regFileEnB <= '1';
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regFileEnB <= '1';
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aluOp <= alu_sum;
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aluOp <= alu_sum;
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regFileWriteAddr <= r2; -- Write data in r2
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regFileWriteAddr <= r2; -- Write data in r2
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muxSel <= fromAlu; -- Select the Alu output
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muxSel <= fromAlu; -- Select the Alu output
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muxRegFile <= muxRegPos(fromRegFileA);
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muxRegFile <= fromRegFileA;
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to 30(10+20)
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-- Read value in r2 to verify if is equal to 30(10+20)
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regFileWriteEn <= '0';
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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inputImm <= (others => 'U');
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| Line 202... |
Line 202... |
regFileReadAddrB <= r0; -- Read data from r0
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regFileReadAddrB <= r0; -- Read data from r0
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regFileEnB <= '1';
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regFileEnB <= '1';
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aluOp <= alu_sum;
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aluOp <= alu_sum;
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regFileWriteAddr <= r3; -- Write data in r2
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regFileWriteAddr <= r3; -- Write data in r2
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muxSel <= fromAlu; -- Select the Alu output
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muxSel <= fromAlu; -- Select the Alu output
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muxRegFile <= muxRegPos(fromRegFileA);
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muxRegFile <= fromRegFileA;
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to 30(10+20)
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-- Read value in r2 to verify if is equal to 30(10+20)
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regFileWriteEn <= '0';
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regFileWriteEn <= '0';
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inputImm <= (others => 'U');
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inputImm <= (others => 'U');
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| Line 226... |
Line 226... |
REPORT "ADD r3,2" SEVERITY NOTE;
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REPORT "ADD r3,2" SEVERITY NOTE;
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inputImm <= conv_std_logic_vector(2, nBits);
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inputImm <= conv_std_logic_vector(2, nBits);
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regFileReadAddrB <= r3; -- Read data from r2
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regFileReadAddrB <= r3; -- Read data from r2
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regFileEnB <= '1';
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regFileEnB <= '1';
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regFileWriteAddr <= r3;
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regFileWriteAddr <= r3;
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muxRegFile <= muxRegPos(fromImediate);
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muxRegFile <= fromImediate;
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aluOp <= alu_sum;
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aluOp <= alu_sum;
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muxSel <= fromAlu; -- Select the Alu output
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muxSel <= fromAlu; -- Select the Alu output
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regFileWriteEn <= '1';
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regFileWriteEn <= '1';
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wait for CLK_period; -- Wait for clock cycle to write into r2
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wait for CLK_period; -- Wait for clock cycle to write into r2
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-- Read value in r2 to verify if is equal to 42(40+2)
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-- Read value in r2 to verify if is equal to 42(40+2)
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