| Line 24... |
Line 24... |
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
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sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
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sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
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END COMPONENT;
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END COMPONENT;
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|
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|
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--Inputs
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--Inputs
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal E : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal E : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal sel : STD_LOGIC_VECTOR (2 downto 0) := "000"; --! Wire to connect Test signal to component
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signal sel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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|
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BEGIN
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BEGIN
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| Line 59... |
Line 59... |
stim_proc: process
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stim_proc: process
|
begin
|
begin
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-- Sel 0 ---------------------------------------------------------------------------
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-- Sel 0 ---------------------------------------------------------------------------
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wait for 1 ps;
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wait for 1 ps;
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REPORT "Select first channel" SEVERITY NOTE;
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REPORT "Select first channel" SEVERITY NOTE;
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sel <= "000";
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sel <= fromMemory;
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A <= conv_std_logic_vector(0, nBits);
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A <= conv_std_logic_vector(0, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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| Line 71... |
Line 71... |
assert S = (A) report "Could not select first channel" severity FAILURE;
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assert S = (A) report "Could not select first channel" severity FAILURE;
|
|
|
-- Sel 1 ---------------------------------------------------------------------------
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-- Sel 1 ---------------------------------------------------------------------------
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wait for 1 ns;
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wait for 1 ns;
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REPORT "Select second channel" SEVERITY NOTE;
|
REPORT "Select second channel" SEVERITY NOTE;
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sel <= "001";
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sel <= fromImediate;
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A <= conv_std_logic_vector(0, nBits);
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A <= conv_std_logic_vector(0, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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| Line 83... |
Line 83... |
assert S = (B) report "Could not select second channel" severity FAILURE;
|
assert S = (B) report "Could not select second channel" severity FAILURE;
|
|
|
-- Sel 2 ---------------------------------------------------------------------------
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-- Sel 2 ---------------------------------------------------------------------------
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wait for 1 ns;
|
wait for 1 ns;
|
REPORT "Select third channel" SEVERITY NOTE;
|
REPORT "Select third channel" SEVERITY NOTE;
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sel <= "010";
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sel <= fromRegFileA;
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A <= conv_std_logic_vector(0, nBits);
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A <= conv_std_logic_vector(0, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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| Line 95... |
Line 95... |
assert S = (C) report "Could not select third channel" severity FAILURE;
|
assert S = (C) report "Could not select third channel" severity FAILURE;
|
|
|
-- Sel 3 ---------------------------------------------------------------------------
|
-- Sel 3 ---------------------------------------------------------------------------
|
wait for 1 ns;
|
wait for 1 ns;
|
REPORT "Select forth channel" SEVERITY NOTE;
|
REPORT "Select forth channel" SEVERITY NOTE;
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sel <= "011";
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sel <= fromRegFileB;
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A <= conv_std_logic_vector(0, nBits);
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A <= conv_std_logic_vector(0, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
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| Line 107... |
Line 107... |
assert S = (D) report "Could not select forth channel" severity FAILURE;
|
assert S = (D) report "Could not select forth channel" severity FAILURE;
|
|
|
-- Sel 4 ---------------------------------------------------------------------------
|
-- Sel 4 ---------------------------------------------------------------------------
|
wait for 1 ns;
|
wait for 1 ns;
|
REPORT "Select fifth channel" SEVERITY NOTE;
|
REPORT "Select fifth channel" SEVERITY NOTE;
|
sel <= "100";
|
sel <= fromAlu;
|
A <= conv_std_logic_vector(0, nBits);
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A <= conv_std_logic_vector(0, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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B <= conv_std_logic_vector(1000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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C <= conv_std_logic_vector(2000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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D <= conv_std_logic_vector(3000, nBits);
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E <= conv_std_logic_vector(4000, nBits);
|
E <= conv_std_logic_vector(4000, nBits);
|
