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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgOpenCPU32.all;
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use work.pkgOpenCPU32.all;
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--! Adding library for File I/O (Synposys Text I/O package)
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--! Adding library for File I/O
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-- More information on this site:
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-- http://eesun.free.fr/DOC/vhdlref/refguide/language_overview/test_benches/reading_and_writing_files_with_text_i_o.htm
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use std.textio.ALL;
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use std.textio.ALL;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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ENTITY testOpenCpu IS
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ENTITY testOpenCpu IS
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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END testOpenCpu;
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END testOpenCpu;
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--! @brief openCpu Testbench file
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--! @brief openCpu Testbench file
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--! @details This is the top-level test...
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--! @details This is the top-level test...
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ARCHITECTURE behavior OF testOpenCpu IS
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ARCHITECTURE behavior OF testOpenCpu IS
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--! Component declaration to instantiate the Multiplexer circuit
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--! Component declaration to instantiate the Multiplexer circuit
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COMPONENT openCpu
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COMPONENT openCpu
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PORT(
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generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
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rst : IN std_logic;
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Port ( rst : in STD_LOGIC; --! Reset signal
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clk : IN std_logic;
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clk : in STD_LOGIC; --! Clock signal
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mem_rd : OUT std_logic;
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mem_rd : out STD_LOGIC; --! Main memory Read enable
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mem_rd_addr : OUT std_logic_vector(31 downto 0);
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mem_rd_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Read address
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mem_wr : OUT std_logic;
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mem_wr : out STD_LOGIC; --! Main memory Write enable
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mem_wr_addr : OUT std_logic_vector(31 downto 0);
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mem_wr_addr : out STD_LOGIC_VECTOR (n downto 0); --! Main memory Write address
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mem_data_in : IN std_logic_vector(31 downto 0);
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mem_data_in : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from main memory
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mem_data_out : OUT std_logic_vector(31 downto 0)
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mem_data_out : out STD_LOGIC_VECTOR (n downto 0) --! Data to main memory
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0';
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal mem_data_in : std_logic_vector(31 downto 0) := (others => '0');
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signal mem_data_in : std_logic_vector(n downto 0) := (others => '0'); --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal mem_rd : std_logic;
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signal mem_rd : std_logic; --! Wire to connect Test signal to component
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signal mem_rd_addr : std_logic_vector(31 downto 0);
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signal mem_rd_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_wr : std_logic;
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signal mem_wr : std_logic; --! Wire to connect Test signal to component
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signal mem_wr_addr : std_logic_vector(31 downto 0);
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signal mem_wr_addr : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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signal mem_data_out : std_logic_vector(31 downto 0);
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signal mem_data_out : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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