| Line 36... |
Line 36... |
--Inputs
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--Inputs
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal clk : std_logic := '0'; --! Wire to connect Test signal to component
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signal writeEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal writeEn : std_logic := '0'; --! Wire to connect Test signal to component
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signal writeAddr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal writeAddr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal input : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal input : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
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signal Read_A_En : std_logic := '0'; --! Wire to connect Test signal to component
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signal Read_A_En : std_logic := 'X'; --! Wire to connect Test signal to component
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signal Read_A_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal Read_A_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal Read_B_En : std_logic := '0'; --! Wire to connect Test signal to component
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signal Read_B_En : std_logic := 'X'; --! Wire to connect Test signal to component
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signal Read_B_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
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signal Read_B_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
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--Outputs
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--Outputs
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signal A_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal A_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal B_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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signal B_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
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| Line 68... |
Line 68... |
--! Process that will stimulate all register assignments, and reads...
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--! Process that will stimulate all register assignments, and reads...
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stim_proc: process
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stim_proc: process
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variable allZ : std_logic_vector((nBits - 1) downto 0) := (others => 'Z');
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variable allZ : std_logic_vector((nBits - 1) downto 0) := (others => 'Z');
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begin
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begin
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-- r0=1 ... r15=16---------------------------------------------------------------------------
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-- r0=1 ... r15=16---------------------------------------------------------------------------
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for i in 0 to (numGenRegs-1) loop
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clk <= '0';
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clk <= '0';
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REPORT "Write r0 := 1" SEVERITY NOTE;
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REPORT "Write r0 := 1" SEVERITY NOTE;
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writeEn <= '1';
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writeEn <= '1';
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writeAddr <= r0;
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writeAddr <= Num2reg(i);
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input <= conv_std_logic_vector(1, nBits);
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input <= conv_std_logic_vector(i+1, nBits);
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wait for 1 ns;
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clk <= '1';
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wait for 1 ns; -- Wait to stabilize the response
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clk <= '0';
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REPORT "Write r1 := 2" SEVERITY NOTE;
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writeEn <= '1';
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writeAddr <= r1;
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input <= conv_std_logic_vector(2, nBits);
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wait for 1 ns;
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clk <= '1';
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wait for 1 ns; -- Wait to stabilize the response
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clk <= '0';
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REPORT "Write r2 := 3" SEVERITY NOTE;
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writeEn <= '1';
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writeAddr <= r2;
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input <= conv_std_logic_vector(3, nBits);
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wait for 1 ns;
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clk <= '1';
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wait for 1 ns; -- Wait to stabilize the response
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clk <= '0';
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REPORT "Write r3 := 4" SEVERITY NOTE;
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writeEn <= '1';
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writeAddr <= r3;
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input <= conv_std_logic_vector(4, nBits);
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wait for 1 ns;
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clk <= '1';
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wait for 1 ns; -- Wait to stabilize the response
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clk <= '0';
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REPORT "Write r4 := 5" SEVERITY NOTE;
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writeEn <= '1';
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writeAddr <= r4;
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input <= conv_std_logic_vector(5, nBits);
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wait for 1 ns;
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wait for 1 ns;
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clk <= '1';
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clk <= '1';
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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end loop;
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-- Mark write end....
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clk <= '0';
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clk <= '0';
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writeEn <= '0';
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writeEn <= '0';
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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-- Read r0..r15 PortA-------------------------------------------------------------------------
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-- Read r0..r15 PortA-------------------------------------------------------------------------
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for i in 0 to (numGenRegs-1) loop
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REPORT "Check r0 = 1" SEVERITY NOTE;
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REPORT "Check r0 = 1" SEVERITY NOTE;
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Read_A_En <= '1';
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Read_A_En <= '1';
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Read_A_Addr <= r0;
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Read_A_Addr <= Num2reg(i);
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert A_Out = conv_std_logic_vector(1, nBits) report "Invalid value r0" severity FAILURE;
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assert A_Out = conv_std_logic_vector(i+1, nBits) report "Invalid value r0" severity FAILURE;
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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end loop;
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REPORT "Check r1 = 2" SEVERITY NOTE;
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-- Mark read A end
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Read_A_En <= '1';
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Read_A_En <= 'X';
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Read_A_Addr <= r1;
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wait for 1 ns; -- Wait to stabilize the response
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assert A_Out = conv_std_logic_vector(2, nBits) report "Invalid value r1" severity FAILURE;
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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REPORT "Check r2 = 3" SEVERITY NOTE;
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-- Read r0..r15 PortB-------------------------------------------------------------------------
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Read_A_En <= '1';
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for i in 0 to (numGenRegs-1) loop
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Read_A_Addr <= r2;
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REPORT "Check r0 = 1" SEVERITY NOTE;
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wait for 1 ns; -- Wait to stabilize the response
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Read_B_En <= '1';
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assert A_Out = conv_std_logic_vector(3, nBits) report "Invalid value r2" severity FAILURE;
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Read_B_Addr <= Num2reg(i);
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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REPORT "Check r3 = 4" SEVERITY NOTE;
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Read_A_En <= '1';
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Read_A_Addr <= r3;
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wait for 1 ns; -- Wait to stabilize the response
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assert A_Out = conv_std_logic_vector(4, nBits) report "Invalid value r3" severity FAILURE;
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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REPORT "Check r4 = 5" SEVERITY NOTE;
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Read_A_En <= '1';
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Read_A_Addr <= r4;
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wait for 1 ns; -- Wait to stabilize the response
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wait for 1 ns; -- Wait to stabilize the response
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assert A_Out = conv_std_logic_vector(5, nBits) report "Invalid value r4" severity FAILURE;
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assert B_Out = conv_std_logic_vector(i+1, nBits) report "Invalid value r0" severity FAILURE;
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assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
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assert A_Out = allZ report "PortB should be high impedance" severity FAILURE;
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end loop;
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-- Mark read B end
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Read_B_En <= 'X';
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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