| Line 73... |
Line 73... |
reset_msr_eip,
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reset_msr_eip,
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`endif
|
`endif
|
`ifdef ENABLE_ALIGNMENT_EXCEPTION
|
`ifdef ENABLE_ALIGNMENT_EXCEPTION
|
dmem_alignment_exception,
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dmem_alignment_exception,
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`endif
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`endif
|
|
`ifdef FSL_LINK
|
|
fsl_m_control, fsl_m_write, fsl_s_read,
|
|
fsl_cmd_vld, fsl_get, fsl_blocking, fsl_control, //FSL
|
|
fsl_m_full, fsl_s_control, fsl_s_exists,
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|
`endif
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clock, reset, stall, // top level
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clock, reset, stall, // top level
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immediate, pc_exe, alu_inputA_sel, alu_inputB_sel, // inputs
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immediate, pc_exe, alu_inputA_sel, alu_inputB_sel, // inputs
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alu_inputC_sel, alu_fns_sel, comparator_fns_sel,
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alu_inputC_sel, alu_fns_sel, comparator_fns_sel,
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we_load, we_store, regA,
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we_load, we_store, regA,
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regB, regD, update_carry, branch_instr,
|
regB, regD, update_carry, branch_instr,
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| Line 127... |
Line 132... |
output insert_exception;
|
output insert_exception;
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`endif
|
`endif
|
`ifdef ENABLE_ALIGNMENT_EXCEPTION
|
`ifdef ENABLE_ALIGNMENT_EXCEPTION
|
input dmem_alignment_exception;
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input dmem_alignment_exception;
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`endif
|
`endif
|
|
`ifdef FSL_LINK
|
|
input fsl_get;
|
|
input fsl_control;
|
|
input fsl_blocking;
|
|
input fsl_cmd_vld;
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input fsl_s_control; //From FSL
|
|
input fsl_s_exists;
|
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input fsl_m_full;
|
|
output fsl_m_control;
|
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output fsl_m_write;
|
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output fsl_s_read;
|
|
`endif
|
|
|
// From REGFILE
|
// From REGFILE
|
input [31:0] regA;
|
input [31:0] regA;
|
input [31:0] regB;
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input [31:0] regB;
|
input [31:0] regD;
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input [31:0] regD;
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| Line 155... |
Line 172... |
reg [31:0] alu_a_input;
|
reg [31:0] alu_a_input;
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reg [31:0] alu_b_input;
|
reg [31:0] alu_b_input;
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reg alu_c_input;
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reg alu_c_input;
|
reg MSB_signed_compare;
|
reg MSB_signed_compare;
|
|
|
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`ifdef FSL_LINK
|
|
reg fsl_complete;
|
|
reg fsl_m_write;
|
|
reg fsl_s_read;
|
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reg fsl_m_control;
|
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`endif
|
|
|
wire alu_multicycle_instr;
|
wire alu_multicycle_instr;
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wire alu_multicycle_instr_complete;
|
wire alu_multicycle_instr_complete;
|
wire multicycle_instr;
|
wire multicycle_instr;
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wire multicycle_instr_complete;
|
wire multicycle_instr_complete;
|
wire c_out;
|
wire c_out;
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| Line 191... |
Line 215... |
wire can_interrupt = // cpu can be interrupted if...
|
wire can_interrupt = // cpu can be interrupted if...
|
`ifdef ENABLE_EXCEPTION
|
`ifdef ENABLE_EXCEPTION
|
~MSR[`MSR_EIP] & // no Exception in Progress
|
~MSR[`MSR_EIP] & // no Exception in Progress
|
`endif
|
`endif
|
`ifdef ENABLE_MSR_BIP
|
`ifdef ENABLE_MSR_BIP
|
~MSR[`MSR_BIP] & ( // no Break in Progress
|
~MSR[`MSR_BIP] & // no Break in Progress
|
`endif
|
|
~int_ip | set_msr_ie // not interrupt in progress
|
|
`ifdef ENABLE_MSR_BIP // and interrupts are enabled
|
|
)
|
|
`endif
|
|
;
|
|
`endif
|
`endif
|
|
(~int_ip | set_msr_ie); // not interrupt in progress
|
|
`endif // and interrupts are enabled
|
|
|
assign branch_taken = branch_instr ? compare_out : 0;
|
assign branch_taken = branch_instr ? compare_out : 0;
|
assign pc_branch = alu_out_internal[`A_SPACE+1:0]; // ALU calculates next instr address
|
assign pc_branch = alu_out_internal[`A_SPACE+1:0]; // ALU calculates next instr address
|
|
|
// instr_complete is always high EXCEPT for optional MUL (alu_multicycle_instr)
|
// instr_complete is always high EXCEPT for optional MUL (alu_multicycle_instr)
|
| Line 213... |
Line 233... |
assign dmem_re = we_load & ~stall;
|
assign dmem_re = we_load & ~stall;
|
|
|
assign memory_instr = we_load | we_store;
|
assign memory_instr = we_load | we_store;
|
assign memory_instr_complete = memory_instr & dmem_done;
|
assign memory_instr_complete = memory_instr & dmem_done;
|
|
|
assign multicycle_instr = memory_instr | alu_multicycle_instr;
|
assign multicycle_instr =
|
assign multicycle_instr_complete = memory_instr_complete | alu_multicycle_instr_complete;
|
`ifdef FSL_LINK
|
|
fsl_cmd_vld |
|
|
`endif
|
|
memory_instr | alu_multicycle_instr;
|
|
assign multicycle_instr_complete =
|
|
`ifdef FSL_LINK
|
|
fsl_complete |
|
|
`endif
|
|
memory_instr_complete | alu_multicycle_instr_complete;
|
|
|
assign instr_complete = ~multicycle_instr | multicycle_instr_complete;
|
assign instr_complete = ~multicycle_instr | multicycle_instr_complete;
|
assign we_regfile = (we_load & dmem_done) | alu_multicycle_instr_complete;
|
assign we_regfile = (we_load & dmem_done) | alu_multicycle_instr_complete;
|
|
|
// for CMP/CMPU
|
// for CMP/CMPU
|
| Line 259... |
Line 287... |
MSR[`MSR_EIP] <= 0; // Exception in Progress
|
MSR[`MSR_EIP] <= 0; // Exception in Progress
|
`endif
|
`endif
|
`ifdef ENABLE_MSR_BIP
|
`ifdef ENABLE_MSR_BIP
|
MSR[`MSR_BIP`] <= 0; // Break In Progress
|
MSR[`MSR_BIP`] <= 0; // Break In Progress
|
`endif
|
`endif
|
|
`ifdef FSL_LINK
|
|
fsl_complete <= 0;
|
|
fsl_m_write <= 0;
|
|
fsl_s_read <= 0;
|
|
`endif
|
end
|
end
|
else if (~stall)
|
else if (~stall)
|
begin
|
begin
|
// Update MSR[BIP] due to BREAK / RTBD
|
// Update MSR[BIP] due to BREAK / RTBD
|
`ifdef ENABLE_MSR_BIP
|
`ifdef ENABLE_MSR_BIP
|
| Line 304... |
Line 337... |
if ((alu_fns_sel == `ALU_add) & update_carry)
|
if ((alu_fns_sel == `ALU_add) & update_carry)
|
MSR[`MSR_C] <= c_out;
|
MSR[`MSR_C] <= c_out;
|
if ((alu_fns_sel == `ALU_shiftR_arth) | (alu_fns_sel == `ALU_shiftR_log) |
|
if ((alu_fns_sel == `ALU_shiftR_arth) | (alu_fns_sel == `ALU_shiftR_log) |
|
(alu_fns_sel == `ALU_shiftR_c))
|
(alu_fns_sel == `ALU_shiftR_c))
|
MSR[`MSR_C] <= regA[0];
|
MSR[`MSR_C] <= regA[0];
|
|
`ifdef FSL_LINK
|
|
// FSL get & put commands
|
|
// Reset control signals after write / read
|
|
if ((fsl_cmd_vld & fsl_complete) | ~fsl_cmd_vld)
|
|
begin
|
|
fsl_s_read <= 0;
|
|
fsl_complete <= 0;
|
|
fsl_m_write <= 0;
|
|
end
|
|
else if (fsl_cmd_vld & ~fsl_get & ~fsl_blocking) // nonblocking put
|
|
begin
|
|
fsl_complete <= 1;
|
|
MSR[`MSR_C] <= fsl_m_full; //**CHECK**
|
|
if (~fsl_m_full)
|
|
begin
|
|
fsl_m_write <= 1;
|
|
fsl_m_control <= fsl_control;
|
|
end
|
|
end
|
|
else if (fsl_cmd_vld & fsl_get & ~fsl_blocking) // nonblocking get
|
|
begin
|
|
fsl_complete <= 1;
|
|
fsl_s_read <= 1;
|
|
MSR[`MSR_C] <= ~fsl_s_exists; //**CHECK**
|
|
if (fsl_s_exists)
|
|
we_load_dly <= 1;
|
|
if (fsl_s_control == fsl_control)
|
|
MSR[`MSR_FSL_Err] <= 0; // MSR[4] = FSL_Error bit
|
|
else
|
|
MSR[`MSR_FSL_Err] <= 1;
|
|
end
|
|
else if (fsl_cmd_vld & ~fsl_get & ~fsl_m_full & fsl_blocking) // blocking put
|
|
begin
|
|
fsl_complete <= 1;
|
|
fsl_m_write <= 1;
|
|
fsl_m_control <= fsl_control;
|
|
end
|
|
else if (fsl_cmd_vld & fsl_get & fsl_s_exists & fsl_blocking) // blocking get
|
|
begin
|
|
fsl_complete <= 1;
|
|
we_load_dly <= 1;
|
|
fsl_s_read <= 1;
|
|
if (fsl_s_control == fsl_control)
|
|
MSR[`MSR_FSL_Err] <= 0;
|
|
else
|
|
MSR[`MSR_FSL_Err] <= 1;
|
|
end
|
|
`endif // End FSL extensions
|
`ifdef DEBUG_EXECUTE
|
`ifdef DEBUG_EXECUTE
|
$display("EXECUTE: pc_exe=%x", pc_exe);
|
$display("EXECUTE: pc_exe=%x", pc_exe);
|
`endif
|
`endif
|
end // end elseif (~stall)
|
end // end elseif (~stall)
|
end // always@
|
end // always@
|
