| Line 181... |
Line 181... |
// REC_HEIGHT - Set rectangle height
|
// REC_HEIGHT - Set rectangle height
|
// {4'b1101, height[11:0]}
|
// {4'b1101, height[11:0]}
|
//
|
//
|
// SRC_PX_ADDR - Set source address
|
// SRC_PX_ADDR - Set source address
|
// {4'b1111, 2'b10, 10'b0000000000}
|
// {4'b1111, 2'b10, 10'b0000000000}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// DST_PX_ADDR - Set destination address
|
// DST_PX_ADDR - Set destination address
|
// {4'b1111, 2'b10, 10'b0000000001}
|
// {4'b1111, 2'b10, 10'b0000000001}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// OF0_ADDR - Set address offset 0
|
// OF0_ADDR - Set address offset 0
|
// {4'b1111, 2'b10, 10'b0000010000}
|
// {4'b1111, 2'b10, 10'b0000010000}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// OF1_ADDR - Set address offset 1
|
// OF1_ADDR - Set address offset 1
|
// {4'b1111, 2'b10, 10'b0000010001}
|
// {4'b1111, 2'b10, 10'b0000010001}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// OF2_ADDR - Set address offset 2
|
// OF2_ADDR - Set address offset 2
|
// {4'b1111, 2'b10, 10'b0000010010}
|
// {4'b1111, 2'b10, 10'b0000010010}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// OF3_ADDR - Set address offset 3
|
// OF3_ADDR - Set address offset 3
|
// {4'b1111, 2'b10, 10'b0000010011}
|
// {4'b1111, 2'b10, 10'b0000010011}
|
// {addr[31:16] }
|
|
// {addr[15:0] }
|
// {addr[15:0] }
|
|
// {addr[31:16] }
|
//
|
//
|
// SET_FILL - Set fill color
|
// SET_FILL - Set fill color
|
// {4'b1111, 2'b01, 10'b0000100000}
|
// {4'b1111, 2'b01, 10'b0000100000}
|
// {fill_color[15:0] }
|
// {fill_color[15:0] }
|
//
|
//
|
| Line 465... |
Line 465... |
// SRC_PX_ADDR_HI Register
|
// SRC_PX_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] src_px_addr_hi;
|
reg [`APIX_HI_MSB:0] src_px_addr_hi;
|
|
|
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) src_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) src_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (src_px_addr_hi_wr) src_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (src_px_addr_hi_wr) src_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 477... |
Line 477... |
//------------------------------------------------
|
//------------------------------------------------
|
// SRC_PX_ADDR_LO Register
|
// SRC_PX_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] src_px_addr_lo;
|
reg [`APIX_LO_MSB:0] src_px_addr_lo;
|
|
|
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) src_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) src_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (src_px_addr_lo_wr) src_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (src_px_addr_lo_wr) src_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign src_px_addr = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
|
assign src_px_addr = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
|
`else
|
`else
|
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MS:0]};
|
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
assign src_px_addr_align = src_px_addr + src_offset_addr;
|
assign src_px_addr_align = src_px_addr + src_offset_addr;
|
assign cfg_src_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {src_px_addr_align[`APIX_MSB:0] } |
|
assign cfg_src_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {src_px_addr_align[`APIX_MSB:0] } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {src_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {src_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
| Line 502... |
Line 502... |
// DST_PX_ADDR_HI Register
|
// DST_PX_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
|
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
|
|
|
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) dst_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) dst_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (dst_px_addr_hi_wr) dst_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (dst_px_addr_hi_wr) dst_px_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 514... |
Line 514... |
//------------------------------------------------
|
//------------------------------------------------
|
// DST_PX_ADDR_LO Register
|
// DST_PX_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
|
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
|
|
|
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
|
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) dst_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) dst_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (dst_px_addr_lo_wr) dst_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (dst_px_addr_lo_wr) dst_px_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign dst_px_addr = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
|
assign dst_px_addr = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
|
`else
|
`else
|
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MS:0]};
|
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
|
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
|
assign cfg_dst_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {dst_px_addr_align[`APIX_MSB:0] } |
|
assign cfg_dst_px_addr_o = {`APIX_MSB+1{gfx_mode_1_bpp }} & {dst_px_addr_align[`APIX_MSB:0] } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {dst_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
{`APIX_MSB+1{gfx_mode_2_bpp }} & {dst_px_addr_align[`APIX_MSB-1:0], 1'b0 } |
|
| Line 539... |
Line 539... |
// OF0_ADDR_HI Register
|
// OF0_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of0_addr_hi;
|
reg [`APIX_HI_MSB:0] of0_addr_hi;
|
|
|
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of0_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of0_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of0_addr_hi_wr) of0_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of0_addr_hi_wr) of0_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 551... |
Line 551... |
//------------------------------------------------
|
//------------------------------------------------
|
// OF0_ADDR_LO Register
|
// OF0_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of0_addr_lo;
|
reg [`APIX_LO_MSB:0] of0_addr_lo;
|
|
|
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of0_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of0_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of0_addr_lo_wr) of0_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of0_addr_lo_wr) of0_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of0_addr = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
|
assign of0_addr = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
|
`else
|
`else
|
assign of0_addr = {of0_addr_lo[`APIX_LO_MS:0]};
|
assign of0_addr = {of0_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF1_ADDR_HI Register
|
// OF1_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of1_addr_hi;
|
reg [`APIX_HI_MSB:0] of1_addr_hi;
|
|
|
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of1_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of1_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of1_addr_hi_wr) of1_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of1_addr_hi_wr) of1_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 581... |
Line 581... |
//------------------------------------------------
|
//------------------------------------------------
|
// OF1_ADDR_LO Register
|
// OF1_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of1_addr_lo;
|
reg [`APIX_LO_MSB:0] of1_addr_lo;
|
|
|
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of1_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of1_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of1_addr_lo_wr) of1_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of1_addr_lo_wr) of1_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of1_addr = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
|
assign of1_addr = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
|
`else
|
`else
|
assign of1_addr = {of1_addr_lo[`APIX_LO_MS:0]};
|
assign of1_addr = {of1_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF2_ADDR_HI Register
|
// OF2_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of2_addr_hi;
|
reg [`APIX_HI_MSB:0] of2_addr_hi;
|
|
|
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of2_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of2_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of2_addr_hi_wr) of2_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of2_addr_hi_wr) of2_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 611... |
Line 611... |
//------------------------------------------------
|
//------------------------------------------------
|
// OF2_ADDR_LO Register
|
// OF2_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of2_addr_lo;
|
reg [`APIX_LO_MSB:0] of2_addr_lo;
|
|
|
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of2_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of2_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of2_addr_lo_wr) of2_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of2_addr_lo_wr) of2_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of2_addr = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
|
assign of2_addr = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
|
`else
|
`else
|
assign of2_addr = {of2_addr_lo[`APIX_LO_MS:0]};
|
assign of2_addr = {of2_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// OF3_ADDR_HI Register
|
// OF3_ADDR_HI Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
reg [`APIX_HI_MSB:0] of3_addr_hi;
|
reg [`APIX_HI_MSB:0] of3_addr_hi;
|
|
|
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
|
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of3_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
if (puc_rst) of3_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
|
else if (of3_addr_hi_wr) of3_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
else if (of3_addr_hi_wr) of3_addr_hi <= gpu_data_i[`APIX_HI_MSB:0];
|
`endif
|
`endif
|
| Line 641... |
Line 641... |
//------------------------------------------------
|
//------------------------------------------------
|
// OF3_ADDR_LO Register
|
// OF3_ADDR_LO Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [`APIX_LO_MSB:0] of3_addr_lo;
|
reg [`APIX_LO_MSB:0] of3_addr_lo;
|
|
|
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
|
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) of3_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
if (puc_rst) of3_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
|
else if (of3_addr_lo_wr) of3_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
else if (of3_addr_lo_wr) of3_addr_lo <= gpu_data_i[`APIX_LO_MSB:0];
|
|
|
`ifdef VRAM_BIGGER_4_KW
|
`ifdef VRAM_BIGGER_4_KW
|
assign of3_addr = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
|
assign of3_addr = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
|
`else
|
`else
|
assign of3_addr = {of3_addr_lo[`APIX_LO_MS:0]};
|
assign of3_addr = {of3_addr_lo[`APIX_LO_MSB:0]};
|
`endif
|
`endif
|
|
|
// Offset address selection
|
// Offset address selection
|
assign src_offset_addr = (src_offset_sel==2'h0) ? of0_addr :
|
assign src_offset_addr = (src_offset_sel==2'h0) ? of0_addr :
|
(src_offset_sel==2'h1) ? of1_addr :
|
(src_offset_sel==2'h1) ? of1_addr :
|
