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Line 374... |
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// LT24 Data
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// LT24 Data
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reg [15:0] lt24_d_nxt;
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reg [15:0] lt24_d_nxt;
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always @(lt24_state_nxt or cmd_generic_cmd_val_i or cmd_generic_param_val_i or lt24_d_o or cmd_dfill_i or refresh_data_i)
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always @(lt24_state_nxt or cmd_generic_cmd_val_i or cmd_generic_param_val_i or lt24_d_o or cmd_dfill_i or refresh_data_i)
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case(lt24_state_nxt)
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case(lt24_state_nxt)
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STATE_IDLE : lt24_d_nxt <= 16'h0000;
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STATE_IDLE : lt24_d_nxt = 16'h0000;
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STATE_CMD_LO,
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STATE_CMD_LO,
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STATE_CMD_HI : lt24_d_nxt <= {8'h00, cmd_generic_cmd_val_i};
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STATE_CMD_HI : lt24_d_nxt = {8'h00, cmd_generic_cmd_val_i};
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STATE_CMD_PARAM_LO,
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STATE_CMD_PARAM_LO,
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STATE_CMD_PARAM_HI : lt24_d_nxt <= cmd_generic_param_val_i;
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STATE_CMD_PARAM_HI : lt24_d_nxt = cmd_generic_param_val_i;
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STATE_CMD_PARAM_WAIT : lt24_d_nxt <= lt24_d_o;
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STATE_CMD_PARAM_WAIT : lt24_d_nxt = lt24_d_o;
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STATE_RAMWR_INIT_CMD_LO,
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STATE_RAMWR_INIT_CMD_LO,
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STATE_RAMWR_INIT_CMD_HI : lt24_d_nxt <= 16'h002C;
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STATE_RAMWR_INIT_CMD_HI : lt24_d_nxt = 16'h002C;
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STATE_RAMWR_INIT_DATA_LO,
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STATE_RAMWR_INIT_DATA_LO,
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STATE_RAMWR_INIT_DATA_HI : lt24_d_nxt <= cmd_dfill_i;
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STATE_RAMWR_INIT_DATA_HI : lt24_d_nxt = cmd_dfill_i;
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STATE_SCANLINE_CMD_LO,
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STATE_SCANLINE_CMD_LO,
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STATE_SCANLINE_CMD_HI : lt24_d_nxt <= 16'h0045;
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STATE_SCANLINE_CMD_HI : lt24_d_nxt = 16'h0045;
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STATE_RAMWR_REFR_CMD_LO,
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STATE_RAMWR_REFR_CMD_LO,
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STATE_RAMWR_REFR_CMD_HI : lt24_d_nxt <= 16'h002C;
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STATE_RAMWR_REFR_CMD_HI : lt24_d_nxt = 16'h002C;
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STATE_RAMWR_REFR_DATA_LO : lt24_d_nxt <= refresh_data_i;
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STATE_RAMWR_REFR_DATA_LO : lt24_d_nxt = refresh_data_i;
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STATE_RAMWR_REFR_DATA_HI : lt24_d_nxt <= lt24_d_o;
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STATE_RAMWR_REFR_DATA_HI : lt24_d_nxt = lt24_d_o;
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STATE_RAMWR_REFR_WAIT : lt24_d_nxt <= lt24_d_o;
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STATE_RAMWR_REFR_WAIT : lt24_d_nxt = lt24_d_o;
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// pragma coverage off
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// pragma coverage off
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default : lt24_d_nxt <= 16'h0000;
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default : lt24_d_nxt = 16'h0000;
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// pragma coverage on
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// pragma coverage on
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endcase
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endcase
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reg [15:0] lt24_d_o;
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reg [15:0] lt24_d_o;
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk or posedge puc_rst)
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Line 433... |
Line 433... |
wire status_gts_lsb_wr = ((lt24_state == STATE_SCANLINE_GTS2_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS2_HI));
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wire status_gts_lsb_wr = ((lt24_state == STATE_SCANLINE_GTS2_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS2_HI));
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always @(posedge mclk or posedge puc_rst)
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always @(posedge mclk or posedge puc_rst)
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if (puc_rst) status_gts_lsb <= 8'h00;
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if (puc_rst) status_gts_lsb <= 8'h00;
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else if (status_gts_lsb_wr) status_gts_lsb <= lt24_d_i[7:0];
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else if (status_gts_lsb_wr) status_gts_lsb <= lt24_d_i[7:0];
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wire [7:0] unused_lt24_d_15_8 = lt24_d_i[15:8];
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wire [9:0] status_gts = {status_gts_msb, status_gts_lsb};
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wire [9:0] status_gts = {status_gts_msb, status_gts_lsb};
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assign status_gts_match = (status_gts == cfg_lt24_refresh_sync_val_i);
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assign status_gts_match = (status_gts == cfg_lt24_refresh_sync_val_i);
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//============================================================================
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//============================================================================
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