| Line 72... |
Line 72... |
gfx_mode_o, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
gfx_mode_o, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
|
|
per_dout_o, // Peripheral data output
|
per_dout_o, // Peripheral data output
|
|
|
refresh_frame_addr_o, // Refresh frame base address
|
refresh_frame_addr_o, // Refresh frame base address
|
refresh_lut_select_o, // Refresh LUT bank selection
|
|
|
hw_lut_palette_sel_o, // Hardware LUT palette configuration
|
|
hw_lut_bgcolor_o, // Hardware LUT background-color selection
|
|
hw_lut_fgcolor_o, // Hardware LUT foreground-color selection
|
|
sw_lut_enable_o, // Refresh LUT-RAM enable
|
|
sw_lut_bank_select_o, // Refresh LUT-RAM bank selection
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
lut_ram_addr_o, // LUT-RAM address
|
lut_ram_addr_o, // LUT-RAM address
|
lut_ram_din_o, // LUT-RAM data
|
lut_ram_din_o, // LUT-RAM data
|
lut_ram_wen_o, // LUT-RAM write strobe (active low)
|
lut_ram_wen_o, // LUT-RAM write strobe (active low)
|
| Line 107... |
Line 112... |
lut_ram_dout_i, // LUT-RAM data input
|
lut_ram_dout_i, // LUT-RAM data input
|
`endif
|
`endif
|
vid_ram_dout_i // Video-RAM data input
|
vid_ram_dout_i // Video-RAM data input
|
);
|
);
|
|
|
|
// PARAMETERs
|
|
//============
|
|
|
|
parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
|
|
// - 7 LSBs must stay cleared: 0x0080, 0x0100,
|
|
// 0x0180, 0x0200,
|
|
// 0x0280, ...
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//============
|
output irq_gfx_o; // Graphic Controller interrupt
|
output irq_gfx_o; // Graphic Controller interrupt
|
|
|
output [15:0] gpu_data_o; // GPU data
|
output [15:0] gpu_data_o; // GPU data
|
output gpu_data_avail_o; // GPU data available
|
output gpu_data_avail_o; // GPU data available
|
output gpu_enable_o; // GPU enable
|
output gpu_enable_o; // GPU enable
|
| Line 140... |
Line 152... |
output [2:0] gfx_mode_o; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
output [2:0] gfx_mode_o; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
|
|
|
output [15:0] per_dout_o; // Peripheral data output
|
output [15:0] per_dout_o; // Peripheral data output
|
|
|
output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
|
output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
|
output [1:0] refresh_lut_select_o; // Refresh LUT bank selection
|
|
|
output [2:0] hw_lut_palette_sel_o; // Hardware LUT palette configuration
|
|
output [3:0] hw_lut_bgcolor_o; // Hardware LUT background-color selection
|
|
output [3:0] hw_lut_fgcolor_o; // Hardware LUT foreground-color selection
|
|
output sw_lut_enable_o; // Refresh LUT-RAM enable
|
|
output sw_lut_bank_select_o; // Refresh LUT-RAM bank selection
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
|
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
|
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
|
output [15:0] lut_ram_din_o; // LUT-RAM data
|
output [15:0] lut_ram_din_o; // LUT-RAM data
|
output lut_ram_wen_o; // LUT-RAM write strobe (active low)
|
output lut_ram_wen_o; // LUT-RAM write strobe (active low)
|
| Line 155... |
Line 172... |
output [15:0] vid_ram_din_o; // Video-RAM data
|
output [15:0] vid_ram_din_o; // Video-RAM data
|
output vid_ram_wen_o; // Video-RAM write strobe (active low)
|
output vid_ram_wen_o; // Video-RAM write strobe (active low)
|
output vid_ram_cen_o; // Video-RAM chip enable (active low)
|
output vid_ram_cen_o; // Video-RAM chip enable (active low)
|
|
|
// INPUTs
|
// INPUTs
|
//=========
|
//============
|
input dbg_freeze_i; // Freeze address auto-incr on read
|
input dbg_freeze_i; // Freeze address auto-incr on read
|
input gpu_cmd_done_evt_i; // GPU command done event
|
input gpu_cmd_done_evt_i; // GPU command done event
|
input gpu_cmd_error_evt_i; // GPU command error event
|
input gpu_cmd_error_evt_i; // GPU command error event
|
input gpu_dma_busy_i; // GPU DMA execution on going
|
input gpu_dma_busy_i; // GPU DMA execution on going
|
input gpu_get_data_i; // GPU get next data
|
input gpu_get_data_i; // GPU get next data
|
| Line 180... |
Line 197... |
|
|
//=============================================================================
|
//=============================================================================
|
// 1) PARAMETER DECLARATION
|
// 1) PARAMETER DECLARATION
|
//=============================================================================
|
//=============================================================================
|
|
|
// Register base address (must be aligned to decoder bit width)
|
|
parameter [14:0] BASE_ADDR = 15'h0200;
|
|
|
|
// Decoder bit width (defines how many bits are considered for address decoding)
|
// Decoder bit width (defines how many bits are considered for address decoding)
|
parameter DEC_WD = 7;
|
parameter DEC_WD = 7;
|
|
|
// Register addresses offset
|
// Register addresses offset
|
parameter [DEC_WD-1:0] GFX_CTRL = 'h00, // General control/status/irq
|
parameter [DEC_WD-1:0] GFX_CTRL = 'h00, // General control/status/irq
|
| Line 206... |
Line 220... |
LT24_CMD = 'h26,
|
LT24_CMD = 'h26,
|
LT24_CMD_PARAM = 'h28,
|
LT24_CMD_PARAM = 'h28,
|
LT24_CMD_DFILL = 'h2A,
|
LT24_CMD_DFILL = 'h2A,
|
LT24_STATUS = 'h2C,
|
LT24_STATUS = 'h2C,
|
|
|
LUT_RAM_ADDR = 'h30, // LUT Memory Access Gate
|
LUT_CFG = 'h30, // LUT Configuration & Memory Access Gate
|
LUT_RAM_DATA = 'h32,
|
LUT_RAM_ADDR = 'h32,
|
|
LUT_RAM_DATA = 'h34,
|
|
|
FRAME_SELECT = 'h3E, // Frame pointers and selection
|
FRAME_SELECT = 'h3E, // Frame pointers and selection
|
FRAME0_PTR_LO = 'h40,
|
FRAME0_PTR_LO = 'h40,
|
FRAME0_PTR_HI = 'h42,
|
FRAME0_PTR_HI = 'h42,
|
FRAME1_PTR_LO = 'h44,
|
FRAME1_PTR_LO = 'h44,
|
| Line 260... |
Line 275... |
LT24_CMD_D = (BASE_REG << LT24_CMD ),
|
LT24_CMD_D = (BASE_REG << LT24_CMD ),
|
LT24_CMD_PARAM_D = (BASE_REG << LT24_CMD_PARAM ),
|
LT24_CMD_PARAM_D = (BASE_REG << LT24_CMD_PARAM ),
|
LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
|
LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
|
LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
|
LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
|
|
|
|
LUT_CFG_D = (BASE_REG << LUT_CFG ),
|
LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
|
LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
|
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
|
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
|
|
|
FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
|
FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
|
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
|
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
|
| Line 320... |
Line 336... |
(LT24_CMD_D & {DEC_SZ{(reg_addr == LT24_CMD )}}) |
|
(LT24_CMD_D & {DEC_SZ{(reg_addr == LT24_CMD )}}) |
|
(LT24_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_CMD_PARAM )}}) |
|
(LT24_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_CMD_PARAM )}}) |
|
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
|
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
|
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
|
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
|
|
|
|
(LUT_CFG_D & {DEC_SZ{(reg_addr == LUT_CFG )}}) |
|
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
|
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
|
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
|
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
|
|
|
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
|
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
|
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
|
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
|
| Line 370... |
Line 387... |
`ifdef WITH_FRAME3_POINTER
|
`ifdef WITH_FRAME3_POINTER
|
wire [`APIX_MSB:0] frame3_ptr;
|
wire [`APIX_MSB:0] frame3_ptr;
|
`endif
|
`endif
|
wire [`APIX_MSB:0] vid_ram0_base_addr;
|
wire [`APIX_MSB:0] vid_ram0_base_addr;
|
wire [`APIX_MSB:0] vid_ram1_base_addr;
|
wire [`APIX_MSB:0] vid_ram1_base_addr;
|
`ifdef WITH_EXTRA_LUT_BANK
|
wire refr_cnt_done_evt;
|
reg lut_bank_select;
|
|
`endif
|
|
wire gpu_fifo_done_evt;
|
wire gpu_fifo_done_evt;
|
wire gpu_fifo_ovfl_evt;
|
wire gpu_fifo_ovfl_evt;
|
|
|
|
|
//============================================================================
|
//============================================================================
|
| Line 395... |
Line 410... |
else if (gfx_ctrl_wr) gfx_ctrl <= per_din_i;
|
else if (gfx_ctrl_wr) gfx_ctrl <= per_din_i;
|
|
|
// Bitfield assignments
|
// Bitfield assignments
|
wire gfx_irq_refr_done_en = gfx_ctrl[0];
|
wire gfx_irq_refr_done_en = gfx_ctrl[0];
|
wire gfx_irq_refr_start_en = gfx_ctrl[1];
|
wire gfx_irq_refr_start_en = gfx_ctrl[1];
|
|
wire gfx_irq_refr_cnt_done_en = gfx_ctrl[2];
|
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
|
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
|
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
|
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
|
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
|
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
|
wire gfx_irq_gpu_cmd_error_en = gfx_ctrl[7];
|
wire gfx_irq_gpu_cmd_error_en = gfx_ctrl[7];
|
assign gfx_mode_o = gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel
|
assign gfx_mode_o = gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel
|
| Line 417... |
Line 433... |
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// GFX_STATUS Register
|
// GFX_STATUS Register
|
//------------------------------------------------
|
//------------------------------------------------
|
wire [15:0] gfx_status;
|
wire [15:0] gfx_status;
|
|
wire gpu_busy;
|
|
|
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
|
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
|
assign gfx_status[15:1] = 15'h0000;
|
assign gfx_status[3:1] = 3'b000;
|
|
assign gfx_status[4] = gpu_data_avail_o;
|
|
assign gfx_status[5] = 1'b0;
|
|
assign gfx_status[6] = gpu_busy;
|
|
assign gfx_status[7] = 1'b0;
|
|
assign gfx_status[15:8] = 15'h0000;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// GFX_IRQ Register
|
// GFX_IRQ Register
|
//------------------------------------------------
|
//------------------------------------------------
|
wire [15:0] gfx_irq;
|
wire [15:0] gfx_irq;
|
| Line 433... |
Line 455... |
wire gfx_irq_refr_done_set = lt24_done_evt_i;
|
wire gfx_irq_refr_done_set = lt24_done_evt_i;
|
|
|
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
|
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
|
wire gfx_irq_refr_start_set = lt24_start_evt_i;
|
wire gfx_irq_refr_start_set = lt24_start_evt_i;
|
|
|
|
wire gfx_irq_refr_cnt_done_clr = per_din_i[2] & reg_wr[GFX_IRQ];
|
|
wire gfx_irq_refr_cnt_done_set = refr_cnt_done_evt;
|
|
|
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
|
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
|
|
|
wire gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;
|
wire gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;
|
| Line 447... |
Line 472... |
wire gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];
|
wire gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;
|
wire gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;
|
|
|
reg gfx_irq_refr_done;
|
reg gfx_irq_refr_done;
|
reg gfx_irq_refr_start;
|
reg gfx_irq_refr_start;
|
|
reg gfx_irq_refr_cnt_done;
|
reg gfx_irq_gpu_fifo_done;
|
reg gfx_irq_gpu_fifo_done;
|
reg gfx_irq_gpu_fifo_ovfl;
|
reg gfx_irq_gpu_fifo_ovfl;
|
reg gfx_irq_gpu_cmd_done;
|
reg gfx_irq_gpu_cmd_done;
|
reg gfx_irq_gpu_cmd_error;
|
reg gfx_irq_gpu_cmd_error;
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst)
|
if (puc_rst)
|
begin
|
begin
|
gfx_irq_refr_done <= 1'b0;
|
gfx_irq_refr_done <= 1'b0;
|
gfx_irq_refr_start <= 1'b0;
|
gfx_irq_refr_start <= 1'b0;
|
|
gfx_irq_refr_cnt_done <= 1'b0;
|
gfx_irq_gpu_fifo_done <= 1'b0;
|
gfx_irq_gpu_fifo_done <= 1'b0;
|
gfx_irq_gpu_fifo_ovfl <= 1'b0;
|
gfx_irq_gpu_fifo_ovfl <= 1'b0;
|
gfx_irq_gpu_cmd_done <= 1'b0;
|
gfx_irq_gpu_cmd_done <= 1'b0;
|
gfx_irq_gpu_cmd_error <= 1'b0;
|
gfx_irq_gpu_cmd_error <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
|
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
|
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
|
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
|
|
gfx_irq_refr_cnt_done <= (gfx_irq_refr_cnt_done_set | (~gfx_irq_refr_cnt_done_clr & gfx_irq_refr_cnt_done)); // IRQ set has priority over clear
|
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
|
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
|
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
|
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
|
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
|
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
|
gfx_irq_gpu_cmd_error <= (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear
|
gfx_irq_gpu_cmd_error <= (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear
|
end
|
end
|
| Line 477... |
Line 505... |
gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,
|
gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,
|
2'h0, gfx_irq_refr_start, gfx_irq_refr_done};
|
2'h0, gfx_irq_refr_start, gfx_irq_refr_done};
|
|
|
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
|
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
|
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
|
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
|
|
(gfx_irq_refr_cnt_done & gfx_irq_refr_cnt_done_en) |
|
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
|
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
|
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
|
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
|
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
|
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
|
(gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en); // Graphic Controller interrupt
|
(gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en); // Graphic Controller interrupt
|
|
|
| Line 589... |
Line 618... |
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) display_refr_cnt <= 16'h0000;
|
if (puc_rst) display_refr_cnt <= 16'h0000;
|
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
|
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
|
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
|
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
|
|
|
|
assign refr_cnt_done_evt = (display_refr_cnt==16'h0001) & display_refr_cnt_dec;
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
// LT24_CFG Register
|
// LT24_CFG Register
|
//------------------------------------------------
|
//------------------------------------------------
|
reg [15:0] lt24_cfg;
|
reg [15:0] lt24_cfg;
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| Line 612... |
Line 643... |
//------------------------------------------------
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//------------------------------------------------
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reg lt24_cmd_refr_o;
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reg lt24_cmd_refr_o;
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reg [11:0] lt24_cfg_refr_o;
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reg [11:0] lt24_cfg_refr_o;
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|
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wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
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wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
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wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==8'h00); // Auto-clear in manual refresh mode when done
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wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==12'h000); // Auto-clear in manual refresh mode when done
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) lt24_cmd_refr_o <= 1'h0;
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if (puc_rst) lt24_cmd_refr_o <= 1'h0;
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else if (lt24_refresh_wr) lt24_cmd_refr_o <= per_din_i[0];
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else if (lt24_refresh_wr) lt24_cmd_refr_o <= per_din_i[0];
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else if (lt24_cmd_refr_clr) lt24_cmd_refr_o <= 1'h0;
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else if (lt24_cmd_refr_clr) lt24_cmd_refr_o <= 1'h0;
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| Line 626... |
Line 657... |
else if (lt24_refresh_wr) lt24_cfg_refr_o <= per_din_i[15:4];
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else if (lt24_refresh_wr) lt24_cfg_refr_o <= per_din_i[15:4];
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wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
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wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
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//------------------------------------------------
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//------------------------------------------------
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// LT24_REFRESH Register
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// LT24_REFRESH_SYNC Register
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//------------------------------------------------
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//------------------------------------------------
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reg lt24_cfg_refr_sync_en_o;
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reg lt24_cfg_refr_sync_en_o;
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reg [9:0] lt24_cfg_refr_sync_val_o;
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reg [9:0] lt24_cfg_refr_sync_val_o;
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wire lt24_refresh_sync_wr = reg_wr[LT24_REFRESH_SYNC];
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wire lt24_refresh_sync_wr = reg_wr[LT24_REFRESH_SYNC];
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| Line 697... |
Line 728... |
assign lt24_status[2] = lt24_status_i[2]; // REFRESH_BUSY
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assign lt24_status[2] = lt24_status_i[2]; // REFRESH_BUSY
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assign lt24_status[3] = lt24_status_i[3]; // WAIT_FOR_SCANLINE
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assign lt24_status[3] = lt24_status_i[3]; // WAIT_FOR_SCANLINE
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assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
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assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
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assign lt24_status[15:5] = 11'h000;
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assign lt24_status[15:5] = 11'h000;
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//------------------------------------------------
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// LUT_CFG Register
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//------------------------------------------------
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wire lut_cfg_wr = reg_wr[LUT_CFG];
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`ifdef WITH_PROGRAMMABLE_LUT
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reg sw_lut_enable_o;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) sw_lut_enable_o <= 1'b0;
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else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
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`ifdef WITH_EXTRA_LUT_BANK
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reg sw_lut_bank_select_o;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) sw_lut_bank_select_o <= 1'b0;
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else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
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`else
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assign sw_lut_bank_select_o = 1'b0;
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`endif
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`else
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assign sw_lut_bank_select_o = 1'b0;
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assign sw_lut_enable_o = 1'b0;
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`endif
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reg [2:0] hw_lut_palette_sel_o;
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always @ (posedge mclk or posedge puc_rst)
|
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if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
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else if (lut_cfg_wr) hw_lut_palette_sel_o <= per_din_i[6:4];
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reg [3:0] hw_lut_bgcolor_o;
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always @ (posedge mclk or posedge puc_rst)
|
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if (puc_rst) hw_lut_bgcolor_o <= 4'h0;
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else if (lut_cfg_wr) hw_lut_bgcolor_o <= per_din_i[11:8];
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reg [3:0] hw_lut_fgcolor_o;
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always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
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else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
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|
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wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
|
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1'b0, hw_lut_palette_sel_o,
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1'b0, sw_lut_bank_select_o, 1'b0, sw_lut_enable_o};
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|
|
//------------------------------------------------
|
//------------------------------------------------
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// LUT_RAM_ADDR Register
|
// LUT_RAM_ADDR Register
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef WITH_PROGRAMMABLE_LUT
|
`ifdef WITH_PROGRAMMABLE_LUT
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|
|
reg [7:0] lut_ram_addr;
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reg [7:0] lut_ram_addr;
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wire [7:0] lut_ram_addr_inc;
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wire [8:0] lut_ram_addr_inc;
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wire lut_ram_addr_inc_wr;
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wire lut_ram_addr_inc_wr;
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|
|
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
|
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
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|
|
always @ (posedge mclk or posedge puc_rst)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc_rst) lut_ram_addr <= 8'h00;
|
if (puc_rst) lut_ram_addr <= 8'h00;
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else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
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else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
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else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc;
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else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc[7:0];
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|
|
|
`ifdef WITH_EXTRA_LUT_BANK
|
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reg lut_bank_select;
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|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) lut_bank_select <= 1'b0;
|
|
else if (lut_ram_addr_wr) lut_bank_select <= per_din_i[8];
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else if (lut_ram_addr_inc_wr) lut_bank_select <= lut_ram_addr_inc[8];
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`else
|
|
wire lut_bank_select = 1'b0;
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|
`endif
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|
|
assign lut_ram_addr_inc = lut_ram_addr + 8'h01;
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assign lut_ram_addr_inc = {lut_bank_select, lut_ram_addr} + 9'h001;
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wire [15:0] lut_ram_addr_rd = {8'h00, lut_ram_addr};
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wire [15:0] lut_ram_addr_rd = {7'h00, lut_bank_select, lut_ram_addr};
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|
|
`ifdef WITH_EXTRA_LUT_BANK
|
`ifdef WITH_EXTRA_LUT_BANK
|
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
|
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
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`else
|
`else
|
assign lut_ram_addr_o = lut_ram_addr;
|
assign lut_ram_addr_o = lut_ram_addr;
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| Line 786... |
Line 870... |
// FRAME_SELECT Register
|
// FRAME_SELECT Register
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
wire frame_select_wr = reg_wr[FRAME_SELECT];
|
wire frame_select_wr = reg_wr[FRAME_SELECT];
|
|
|
`ifdef WITH_PROGRAMMABLE_LUT
|
|
reg refresh_sw_lut_enable;
|
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst) refresh_sw_lut_enable <= 1'b0;
|
|
else if (frame_select_wr) refresh_sw_lut_enable <= per_din_i[2];
|
|
`else
|
|
wire refresh_sw_lut_enable = 1'b0;
|
|
`endif
|
|
|
|
`ifdef WITH_EXTRA_LUT_BANK
|
|
reg refresh_sw_lut_select;
|
|
|
|
always @ (posedge mclk or posedge puc_rst)
|
|
if (puc_rst)
|
|
begin
|
|
refresh_sw_lut_select <= 1'b0;
|
|
lut_bank_select <= 1'b0;
|
|
end
|
|
else if (frame_select_wr)
|
|
begin
|
|
refresh_sw_lut_select <= per_din_i[3];
|
|
lut_bank_select <= per_din_i[15];
|
|
end
|
|
`else
|
|
assign refresh_sw_lut_select = 1'b0;
|
|
wire lut_bank_select = 1'b0;
|
|
`endif
|
|
wire [1:0] refresh_lut_select_o = {refresh_sw_lut_select, refresh_sw_lut_enable};
|
|
|
|
`ifdef WITH_FRAME1_POINTER
|
`ifdef WITH_FRAME1_POINTER
|
`ifdef WITH_FRAME2_POINTER
|
`ifdef WITH_FRAME2_POINTER
|
reg [1:0] refresh_frame_select;
|
reg [1:0] refresh_frame_select;
|
reg [1:0] vid_ram0_frame_select;
|
reg [1:0] vid_ram0_frame_select;
|
reg [1:0] vid_ram1_frame_select;
|
reg [1:0] vid_ram1_frame_select;
|
| Line 836... |
Line 890... |
refresh_frame_select <= per_din_i[1:0];
|
refresh_frame_select <= per_din_i[1:0];
|
vid_ram0_frame_select <= per_din_i[5:4];
|
vid_ram0_frame_select <= per_din_i[5:4];
|
vid_ram1_frame_select <= per_din_i[7:6];
|
vid_ram1_frame_select <= per_din_i[7:6];
|
end
|
end
|
|
|
wire [15:0] frame_select = {lut_bank_select, 7'h00, vid_ram1_frame_select, vid_ram0_frame_select, refresh_lut_select_o, refresh_frame_select};
|
wire [15:0] frame_select = {8'h00, vid_ram1_frame_select, vid_ram0_frame_select, 2'h0, refresh_frame_select};
|
`else
|
`else
|
reg refresh_frame_select;
|
reg refresh_frame_select;
|
reg vid_ram0_frame_select;
|
reg vid_ram0_frame_select;
|
reg vid_ram1_frame_select;
|
reg vid_ram1_frame_select;
|
|
|
| Line 856... |
Line 910... |
refresh_frame_select <= per_din_i[0];
|
refresh_frame_select <= per_din_i[0];
|
vid_ram0_frame_select <= per_din_i[4];
|
vid_ram0_frame_select <= per_din_i[4];
|
vid_ram1_frame_select <= per_din_i[6];
|
vid_ram1_frame_select <= per_din_i[6];
|
end
|
end
|
|
|
wire [15:0] frame_select = {lut_bank_select, 7'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, refresh_lut_select_o, 1'h0, refresh_frame_select};
|
wire [15:0] frame_select = {8'h00, 1'h0, vid_ram1_frame_select, 1'h0, vid_ram0_frame_select, 2'h0, 1'h0, refresh_frame_select};
|
`endif
|
`endif
|
`else
|
`else
|
wire [15:0] frame_select = {lut_bank_select, 11'h000, refresh_lut_select_o, 2'h0};
|
wire [15:0] frame_select = 16'h0000;
|
`endif
|
`endif
|
|
|
// Frame pointer selections
|
// Frame pointer selections
|
`ifdef WITH_FRAME1_POINTER
|
`ifdef WITH_FRAME1_POINTER
|
assign refresh_frame_addr_o = (refresh_frame_select==0) ? frame0_ptr :
|
assign refresh_frame_addr_o = (refresh_frame_select==0) ? frame0_ptr :
|
| Line 1216... |
Line 1270... |
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
|
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
|
);
|
);
|
|
|
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
|
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
|
|
|
wire gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
|
assign gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
|
|
|
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
|
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
|
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
|
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
|
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
|
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
|
|
|
| Line 1249... |
Line 1303... |
wire [15:0] lt24_cmd_read = lt24_cmd & {16{reg_rd[LT24_CMD ]}};
|
wire [15:0] lt24_cmd_read = lt24_cmd & {16{reg_rd[LT24_CMD ]}};
|
wire [15:0] lt24_cmd_param_read = lt24_cmd_param_o & {16{reg_rd[LT24_CMD_PARAM ]}};
|
wire [15:0] lt24_cmd_param_read = lt24_cmd_param_o & {16{reg_rd[LT24_CMD_PARAM ]}};
|
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
|
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
|
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
|
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
|
|
|
|
wire [15:0] lut_cfg_read = lut_cfg_rd & {16{reg_rd[LUT_CFG ]}};
|
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
|
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
|
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
|
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
|
|
|
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
|
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
|
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
|
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
|
| Line 1316... |
Line 1371... |
lt24_cmd_read |
|
lt24_cmd_read |
|
lt24_cmd_param_read |
|
lt24_cmd_param_read |
|
lt24_cmd_dfill_read |
|
lt24_cmd_dfill_read |
|
lt24_status_read |
|
lt24_status_read |
|
|
|
|
lut_cfg_read |
|
lut_ram_addr_read |
|
lut_ram_addr_read |
|
lut_ram_data_read |
|
lut_ram_data_read |
|
|
|
frame_select_read |
|
frame_select_read |
|
frame0_ptr_lo_read |
|
frame0_ptr_lo_read |
|
