| Line 740... |
Line 740... |
reg sw_lut_enable_o;
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reg sw_lut_enable_o;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) sw_lut_enable_o <= 1'b0;
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if (puc_rst) sw_lut_enable_o <= 1'b0;
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else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
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else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
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reg sw_lut_ram_rmw_mode;
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) sw_lut_ram_rmw_mode <= 1'b0;
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else if (lut_cfg_wr) sw_lut_ram_rmw_mode <= per_din_i[1];
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`ifdef WITH_EXTRA_LUT_BANK
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`ifdef WITH_EXTRA_LUT_BANK
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reg sw_lut_bank_select_o;
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reg sw_lut_bank_select_o;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) sw_lut_bank_select_o <= 1'b0;
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if (puc_rst) sw_lut_bank_select_o <= 1'b0;
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else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
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else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
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| Line 751... |
Line 756... |
assign sw_lut_bank_select_o = 1'b0;
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assign sw_lut_bank_select_o = 1'b0;
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`endif
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`endif
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`else
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`else
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assign sw_lut_bank_select_o = 1'b0;
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assign sw_lut_bank_select_o = 1'b0;
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assign sw_lut_enable_o = 1'b0;
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assign sw_lut_enable_o = 1'b0;
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wire sw_lut_ram_rmw_mode = 1'b0;
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`endif
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`endif
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reg [2:0] hw_lut_palette_sel_o;
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reg [2:0] hw_lut_palette_sel_o;
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always @ (posedge mclk or posedge puc_rst)
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always @ (posedge mclk or posedge puc_rst)
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if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
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if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
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| Line 770... |
Line 776... |
if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
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if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
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else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
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else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
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wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
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wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
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1'b0, hw_lut_palette_sel_o,
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1'b0, hw_lut_palette_sel_o,
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1'b0, sw_lut_bank_select_o, 1'b0, sw_lut_enable_o};
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1'b0, sw_lut_bank_select_o,
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sw_lut_ram_rmw_mode, sw_lut_enable_o};
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//------------------------------------------------
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//------------------------------------------------
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// LUT_RAM_ADDR Register
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// LUT_RAM_ADDR Register
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//------------------------------------------------
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//------------------------------------------------
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`ifdef WITH_PROGRAMMABLE_LUT
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`ifdef WITH_PROGRAMMABLE_LUT
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| Line 829... |
Line 836... |
if (puc_rst) lut_ram_data <= 16'h0000;
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if (puc_rst) lut_ram_data <= 16'h0000;
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else if (lut_ram_data_wr) lut_ram_data <= per_din_i;
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else if (lut_ram_data_wr) lut_ram_data <= per_din_i;
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else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
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else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
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// Increment the address after a write or read access to the LUT_RAM_DATA register
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// Increment the address after a write or read access to the LUT_RAM_DATA register
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assign lut_ram_addr_inc_wr = lut_ram_data_wr | lut_ram_data_rd;
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// - one clock cycle after a write access
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// - with the read access (if not in read-modify-write mode)
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assign lut_ram_addr_inc_wr = lut_ram_data_wr | (lut_ram_data_rd & ~dbg_freeze_i & ~sw_lut_ram_rmw_mode);
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// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
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// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
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assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
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assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
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assign lut_ram_wen_o = ~(|per_we_i & lut_ram_data_wr);
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assign lut_ram_wen_o = ~(|per_we_i & lut_ram_data_wr);
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