| Line 33... |
Line 33... |
*
|
*
|
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
|
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
|
*
|
*
|
*
|
*
|
* Module name: hmc_controller_top
|
* Module name: openhmc_top
|
*
|
*
|
|
*
|
|
*
|
|
*
|
|
* DESIGN CONTROL: Use the following defines if desired:
|
|
* `define XILINX
|
|
* Uses Xilinx DSP48 as counter in the Register File
|
|
* `define ASYNC_RES
|
|
* Define the active low reset to be asynchronous
|
|
* `define RESET_ALL
|
|
* Use Reset values for all registers
|
*/
|
*/
|
|
|
`default_nettype none
|
`default_nettype none
|
|
|
module openhmc_top #(
|
module openhmc_top #(
|
//Define width of the datapath
|
//Define width of the datapath
|
parameter LOG_FPW = 2, //Legal Values: 1,2,3
|
|
parameter FPW = 4, //Legal Values: 2,4,6,8
|
parameter FPW = 4, //Legal Values: 2,4,6,8
|
|
parameter LOG_FPW = 2, //Legal Values: 1 for FPW=2 ,2 for FPW=4 ,3 for FPW=6/8
|
parameter DWIDTH = FPW*128, //Leave untouched
|
parameter DWIDTH = FPW*128, //Leave untouched
|
//Define HMC interface width
|
//Define HMC interface width
|
parameter LOG_NUM_LANES = 3, //Set 3 for half-width, 4 for full-width
|
parameter LOG_NUM_LANES = 3, //Set 3 for half-width, 4 for full-width
|
parameter NUM_LANES = 2**LOG_NUM_LANES, //Leave untouched
|
parameter NUM_LANES = 2**LOG_NUM_LANES, //Leave untouched
|
parameter NUM_DATA_BYTES = FPW*16, //Leave untouched
|
parameter NUM_DATA_BYTES = FPW*16, //Leave untouched
|
//Define width of the register file
|
//Define width of the register file
|
parameter HMC_RF_WWIDTH = 64,
|
parameter HMC_RF_WWIDTH = 64, //Leave untouched
|
parameter HMC_RF_RWIDTH = 64,
|
parameter HMC_RF_RWIDTH = 64, //Leave untouched
|
parameter HMC_RF_AWIDTH = 4,
|
parameter HMC_RF_AWIDTH = 4, //Leave untouched
|
//Configure the Functionality
|
//Configure the Functionality
|
parameter LOG_MAX_RTC = 8, //Set the depth of the RX input buffer. Must be >= LOG(rf_rx_buffer_rtc) in the RF
|
parameter LOG_MAX_RX_TOKENS = 8, //Set the depth of the RX input buffer. Must be >= LOG(rf_rx_buffer_rtc) in the RF. Dont't care if OPEN_RSP_MODE=1
|
parameter HMC_RX_AC_COUPLED = 1, //Set to 0 to remove the run length limiter, saves logic and 1 cycle delay
|
parameter LOG_MAX_HMC_TOKENS = 10, //Set the depth of the HMC input buffer. Must be >= LOG of the corresponding field in the HMC internal register
|
|
parameter HMC_RX_AC_COUPLED = 1, //Set to 0 to bypass the run length limiter, saves logic and 1 cycle delay
|
|
parameter DETECT_LANE_POLARITY = 1, //Set to 0 if lane polarity is not applicable, saves logic
|
parameter CTRL_LANE_POLARITY = 1, //Set to 0 if lane polarity is not applicable or performed by the transceivers, saves logic and 1 cycle delay
|
parameter CTRL_LANE_POLARITY = 1, //Set to 0 if lane polarity is not applicable or performed by the transceivers, saves logic and 1 cycle delay
|
|
//If set to 1: Only valid if DETECT_LANE_POLARITY==1, otherwise tied to zero
|
parameter CTRL_LANE_REVERSAL = 1, //Set to 0 if lane reversal is not applicable or performed by the transceivers, saves logic
|
parameter CTRL_LANE_REVERSAL = 1, //Set to 0 if lane reversal is not applicable or performed by the transceivers, saves logic
|
|
parameter CTRL_SCRAMBLERS = 1, //Set to 0 to remove the option to disable (de-)scramblers for debugging, saves logic
|
|
parameter OPEN_RSP_MODE = 0, //Set to 1 if running response open loop mode, bypasses the RX input buffer
|
|
parameter RX_RELAX_INIT_TIMING = 1, //Per default, incoming TS1 sequences are only checked for the lane independent h'F0 sequence. Save resources and
|
|
//eases timing closure. !Lane reversal is still detected
|
|
parameter RX_BIT_SLIP_CNT_LOG = 5, //Define the number of cycles between bit slips. Refer to the transceiver user guide
|
|
//Example: RX_BIT_SLIP_CNT_LOG=5 results in 2^5=32 cycles between two bit slips
|
|
parameter SYNC_AXI4_IF = 0, //Set to 1 if AXI IF is synchronous to clk_hmc to use simple fifos
|
|
parameter XIL_CNT_PIPELINED = 1, //If Xilinx counters are used, set to 1 to enabled output register pipelining
|
//Set the direction of bitslip. Set to 1 if bitslip performs a shift right, otherwise set to 0 (see the corresponding transceiver user guide)
|
//Set the direction of bitslip. Set to 1 if bitslip performs a shift right, otherwise set to 0 (see the corresponding transceiver user guide)
|
parameter BITSLIP_SHIFT_RIGHT = 1,
|
parameter BITSLIP_SHIFT_RIGHT = 1,
|
//Debug Params
|
//Debug Params
|
parameter DBG_RX_TOKEN_MON = 1 //Remove the RX Link token monitor, saves logic
|
parameter DBG_RX_TOKEN_MON = 1 //Set to 0 to remove the RX Link token monitor, saves logic
|
) (
|
) (
|
//----------------------------------
|
//----------------------------------
|
//----SYSTEM INTERFACES
|
//----SYSTEM INTERFACES
|
//----------------------------------
|
//----------------------------------
|
input wire clk_user,
|
input wire clk_user, //Connect if SYNC_AXI4_IF==0
|
input wire clk_hmc,
|
input wire clk_hmc, //Connect!
|
input wire res_n_user,
|
input wire res_n_user, //Connect if SYNC_AXI4_IF==0
|
input wire res_n_hmc,
|
input wire res_n_hmc, //Connect!
|
|
|
//----------------------------------
|
//----------------------------------
|
//----Connect AXI Ports
|
//----Connect AXI Ports
|
//----------------------------------
|
//----------------------------------
|
//From AXI to HMC Ctrl TX
|
//From AXI to HMC Ctrl TX
|
| Line 87... |
Line 108... |
output wire [NUM_DATA_BYTES-1:0] m_axis_rx_TUSER,
|
output wire [NUM_DATA_BYTES-1:0] m_axis_rx_TUSER,
|
|
|
//----------------------------------
|
//----------------------------------
|
//----Connect Transceiver
|
//----Connect Transceiver
|
//----------------------------------
|
//----------------------------------
|
output wire [DWIDTH-1:0] phy_data_tx_link2phy,
|
output wire [DWIDTH-1:0] phy_data_tx_link2phy,//Connect!
|
input wire [DWIDTH-1:0] phy_data_rx_phy2link,
|
input wire [DWIDTH-1:0] phy_data_rx_phy2link,//Connect!
|
output wire [NUM_LANES-1:0] phy_bit_slip,
|
output wire [NUM_LANES-1:0] phy_bit_slip, //Must be connected if DETECT_LANE_POLARITY==1 AND CTRL_LANE_POLARITY=0
|
output wire [NUM_LANES-1:0] phy_lane_polarity, //All 0 if CTRL_LANE_POLARITY=1
|
output wire [NUM_LANES-1:0] phy_lane_polarity, //All 0 if CTRL_LANE_POLARITY=1
|
input wire phy_ready,
|
input wire phy_tx_ready, //Optional information to RF
|
|
input wire phy_rx_ready, //Release RX descrambler reset when PHY ready
|
|
output wire phy_init_cont_set, //Can be used to release transceiver reset if used
|
|
|
//----------------------------------
|
//----------------------------------
|
//----Connect HMC
|
//----Connect HMC
|
//----------------------------------
|
//----------------------------------
|
output wire P_RST_N,
|
output wire P_RST_N,
|
output wire hmc_LxRXPS,
|
output wire LXRXPS,
|
input wire hmc_LxTXPS,
|
input wire LXTXPS,
|
input wire FERR_N, //Not connected
|
input wire FERR_N,
|
|
|
//----------------------------------
|
//----------------------------------
|
//----Connect RF
|
//----Connect RF
|
//----------------------------------
|
//----------------------------------
|
input wire [HMC_RF_AWIDTH-1:0] rf_address,
|
input wire [HMC_RF_AWIDTH-1:0] rf_address,
|
| Line 120... |
Line 143... |
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
|
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//=====================================================================================================
|
//=====================================================================================================
|
|
|
|
localparam MAX_RTC_RET_LOG = (FPW == 2) ? 6 :
|
|
(FPW == 4) ? 7 :
|
|
8;
|
|
|
|
`ifdef XILINX
|
|
localparam RF_COUNTER_SIZE = 48;
|
|
`else
|
|
localparam RF_COUNTER_SIZE = 64;
|
|
`endif
|
|
|
// ----Assign AXI interface wires
|
// ----Assign AXI interface wires
|
wire [4*FPW-1:0] m_axis_rx_TUSER_temp;
|
wire [4*FPW-1:0] m_axis_rx_TUSER_temp;
|
assign m_axis_rx_TUSER = {{NUM_DATA_BYTES-(4*FPW){1'b0}}, m_axis_rx_TUSER_temp};
|
assign m_axis_rx_TUSER = {{NUM_DATA_BYTES-(4*FPW){1'b0}}, m_axis_rx_TUSER_temp};
|
|
|
wire s_axis_tx_TREADY_n;
|
wire s_axis_tx_TREADY_n;
|
assign s_axis_tx_TREADY = ~s_axis_tx_TREADY_n;
|
assign s_axis_tx_TREADY = ~s_axis_tx_TREADY_n;
|
|
|
wire m_axis_rx_TVALID_n;
|
wire m_axis_rx_TVALID_n;
|
assign m_axis_rx_TVALID = ~m_axis_rx_TVALID_n;
|
assign m_axis_rx_TVALID = ~m_axis_rx_TVALID_n;
|
|
|
// ----TX FIFO Wires
|
// ----TX FIFO Wires
|
wire [DWIDTH-1:0] tx_d_in_data;
|
wire [DWIDTH-1:0] tx_d_in_data;
|
| Line 140... |
Line 172... |
wire [3*FPW-1:0] tx_d_in_ctrl;
|
wire [3*FPW-1:0] tx_d_in_ctrl;
|
|
|
// ----RX FIFO Wires
|
// ----RX FIFO Wires
|
wire [DWIDTH-1:0] rx_d_in_data;
|
wire [DWIDTH-1:0] rx_d_in_data;
|
wire rx_shift_in;
|
wire rx_shift_in;
|
wire rx_full;
|
|
wire rx_a_full;
|
wire rx_a_full;
|
wire [4*FPW-1:0] rx_d_in_ctrl;
|
wire [4*FPW-1:0] rx_d_in_ctrl;
|
|
|
// ----RX LINK TO TX LINK
|
// ----RX LINK TO TX LINK
|
wire rx2tx_link_retry;
|
wire rx2tx_link_retry;
|
wire rx2tx_error_abort_mode;
|
wire rx2tx_error_abort_mode;
|
wire rx2tx_error_abort_mode_cleared;
|
wire rx2tx_error_abort_mode_cleared;
|
wire [7:0] rx2tx_hmc_frp;
|
wire [7:0] rx2tx_hmc_frp;
|
wire [7:0] rx2tx_rrp;
|
wire [7:0] rx2tx_rrp;
|
wire [7:0] rx2tx_returned_tokens;
|
wire [MAX_RTC_RET_LOG-1:0]rx2tx_returned_tokens;
|
wire [LOG_FPW:0] rx2tx_hmc_tokens_to_return;
|
wire [LOG_FPW:0] rx2tx_hmc_tokens_to_return;
|
wire [LOG_FPW:0] rx2tx_hmc_poisoned_tokens_to_return;
|
wire [LOG_FPW:0] rx2tx_hmc_poisoned_tokens_to_return;
|
|
|
// ----Register File
|
// ----Register File
|
//Counter
|
//Counter
|
wire rf_cnt_retry;
|
wire rf_cnt_retry;
|
wire rf_run_length_bit_flip;
|
wire rf_run_length_bit_flip;
|
wire rf_error_abort_not_cleared;
|
wire rf_error_abort_not_cleared;
|
wire [HMC_RF_RWIDTH-1:0] rf_cnt_poisoned;
|
wire [RF_COUNTER_SIZE-1:0] rf_cnt_poisoned;
|
wire [HMC_RF_RWIDTH-1:0] rf_cnt_p;
|
wire [RF_COUNTER_SIZE-1:0] rf_cnt_p;
|
wire [HMC_RF_RWIDTH-1:0] rf_cnt_np;
|
wire [RF_COUNTER_SIZE-1:0] rf_cnt_np;
|
wire [HMC_RF_RWIDTH-1:0] rf_cnt_r;
|
wire [RF_COUNTER_SIZE-1:0] rf_cnt_r;
|
wire [HMC_RF_RWIDTH-1:0] rf_cnt_rsp_rcvd;
|
wire [RF_COUNTER_SIZE-1:0] rf_cnt_rsp_rcvd;
|
//Status
|
//Status
|
wire [1:0] rf_link_status;
|
wire rf_link_up;
|
wire [2:0] rf_hmc_init_status;
|
wire [2:0] rf_rx_init_status;
|
wire [1:0] rf_tx_init_status;
|
wire [1:0] rf_tx_init_status;
|
wire [9:0] rf_hmc_tokens_av;
|
wire [LOG_MAX_HMC_TOKENS-1:0]rf_hmc_tokens_av;
|
wire [9:0] rf_rx_tokens_av;
|
wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_tokens_av;
|
wire rf_hmc_sleep;
|
|
//Init Status
|
//Init Status
|
wire rf_all_descramblers_aligned;
|
wire rf_all_descramblers_aligned;
|
wire [NUM_LANES-1:0] rf_descrambler_aligned;
|
wire [NUM_LANES-1:0] rf_descrambler_aligned;
|
wire [NUM_LANES-1:0] rf_descrambler_part_aligned;
|
wire [NUM_LANES-1:0] rf_descrambler_part_aligned;
|
//Control
|
//Control
|
wire [5:0] rf_bit_slip_time;
|
|
wire rf_hmc_init_cont_set;
|
wire rf_hmc_init_cont_set;
|
wire rf_set_hmc_sleep;
|
wire rf_set_hmc_sleep;
|
|
wire rf_warm_reset;
|
wire rf_scrambler_disable;
|
wire rf_scrambler_disable;
|
wire [NUM_LANES-1:0] rf_lane_polarity;
|
wire [NUM_LANES-1:0] rf_lane_polarity;
|
wire [NUM_LANES-1:0] rf_descramblers_locked;
|
wire [NUM_LANES-1:0] rf_descramblers_locked;
|
wire [9:0] rf_rx_buffer_rtc;
|
wire [LOG_MAX_RX_TOKENS-1:0]rf_rx_buffer_rtc;
|
wire rf_lane_reversal_detected;
|
wire rf_lane_reversal_detected;
|
wire [4:0] rf_irtry_received_threshold;
|
wire [4:0] rf_irtry_received_threshold;
|
wire [4:0] rf_irtry_to_send;
|
wire [4:0] rf_irtry_to_send;
|
wire rf_run_length_enable;
|
wire rf_run_length_enable;
|
wire [2:0] rf_first_cube_ID;
|
|
//Debug
|
assign phy_init_cont_set = rf_hmc_init_cont_set;
|
wire rf_dbg_dont_send_tret;
|
|
wire rf_dbg_halt_on_error_abort;
|
//Generate
|
wire rf_dbg_halt_on_tx_retry;
|
wire rf_scrambler_disable_temp;
|
|
wire [LOG_MAX_RX_TOKENS-1:0] rf_rx_buffer_rtc_temp;
|
|
generate
|
|
if(CTRL_SCRAMBLERS==1) begin : ctrl_scramblers
|
|
assign rf_scrambler_disable = rf_scrambler_disable_temp;
|
|
end else begin : remove_scrambler_disable_bit
|
|
assign rf_scrambler_disable = 1'b0;
|
|
end
|
|
if(OPEN_RSP_MODE==1) begin : remove_rx_tokens_rsp_open_loop_mode
|
|
assign rf_rx_buffer_rtc = {LOG_MAX_RX_TOKENS{1'b0}};
|
|
end else begin : regular_mode_use_rx_tokens
|
|
assign rf_rx_buffer_rtc = rf_rx_buffer_rtc_temp;
|
|
end
|
|
endgenerate
|
|
|
// ----Assign PHY wires
|
// ----Assign PHY wires
|
assign phy_lane_polarity = (CTRL_LANE_POLARITY==1) ? {NUM_LANES{1'b0}} : rf_lane_polarity;
|
assign phy_lane_polarity = (CTRL_LANE_POLARITY==1) ? {NUM_LANES{1'b0}} : rf_lane_polarity;
|
|
|
//=====================================================================================================
|
//=====================================================================================================
|
| Line 204... |
Line 247... |
//-----------------------------------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------------------------------
|
//=====================================================================================================
|
//=====================================================================================================
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX
|
//-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX-----TX
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
|
generate
|
|
if(SYNC_AXI4_IF==0) begin : async_axi4_tx_fifo
|
openhmc_async_fifo #(
|
openhmc_async_fifo #(
|
.DWIDTH(DWIDTH+(FPW*3)),
|
.DWIDTH(DWIDTH+(FPW*3)),
|
.ENTRIES(16)
|
.ENTRIES(16)
|
) fifo_tx_data (
|
) fifo_tx_data (
|
//System
|
//System
|
| Line 227... |
Line 271... |
.d_out({tx_d_in_ctrl,tx_d_in_data}),
|
.d_out({tx_d_in_ctrl,tx_d_in_data}),
|
.shift_out(tx_shift_out),
|
.shift_out(tx_shift_out),
|
.empty(tx_empty),
|
.empty(tx_empty),
|
.almost_empty(tx_a_empty)
|
.almost_empty(tx_a_empty)
|
);
|
);
|
|
end else begin : synchronous_axi4_tx_fifo
|
|
`ifdef XILINX
|
|
openhmc_sync_fifo_xilinx #(
|
|
.DWIDTH(DWIDTH+(FPW*3))
|
|
) fifo_tx_data_sync_xilinx(
|
|
//System
|
|
.clk(clk_hmc),
|
|
.res_n(res_n_hmc),
|
|
|
|
//To RX LINK Logic
|
|
.d_in({s_axis_tx_TUSER[(FPW*3)-1:0],s_axis_tx_TDATA}),
|
|
.shift_in(s_axis_tx_TVALID && s_axis_tx_TREADY),
|
|
.full(s_axis_tx_TREADY_n),
|
|
.almost_full(),
|
|
|
|
//AXI-4 RX IF
|
|
.d_out({tx_d_in_ctrl,tx_d_in_data}),
|
|
.shift_out(tx_shift_out),
|
|
.empty(tx_empty),
|
|
.almost_empty(tx_a_empty)
|
|
);
|
|
`else
|
|
openhmc_sync_fifo_reg_based #(
|
|
.DWIDTH(DWIDTH+(FPW*3)),
|
|
.ENTRIES(4)
|
|
) fifo_tx_data_sync(
|
|
//System
|
|
.clk(clk_hmc),
|
|
.res_n(res_n_hmc),
|
|
|
|
//To RX LINK Logic
|
|
.d_in({s_axis_tx_TUSER[(FPW*3)-1:0],s_axis_tx_TDATA}),
|
|
.shift_in(s_axis_tx_TVALID && s_axis_tx_TREADY),
|
|
.full(s_axis_tx_TREADY_n),
|
|
.almost_full(),
|
|
|
|
//AXI-4 RX IF
|
|
.d_out({tx_d_in_ctrl,tx_d_in_data}),
|
|
.shift_out(tx_shift_out),
|
|
.empty(tx_empty),
|
|
.almost_empty(tx_a_empty)
|
|
);
|
|
`endif
|
|
end
|
|
endgenerate
|
|
|
|
|
tx_link #(
|
tx_link #(
|
.LOG_FPW(LOG_FPW),
|
.LOG_FPW(LOG_FPW),
|
.FPW(FPW),
|
.FPW(FPW),
|
.NUM_LANES(NUM_LANES),
|
.NUM_LANES(NUM_LANES),
|
.HMC_PTR_SIZE(8),
|
.RF_COUNTER_SIZE(RF_COUNTER_SIZE),
|
.HMC_RF_RWIDTH(HMC_RF_RWIDTH),
|
|
.HMC_RX_AC_COUPLED(HMC_RX_AC_COUPLED),
|
.HMC_RX_AC_COUPLED(HMC_RX_AC_COUPLED),
|
|
.MAX_RTC_RET_LOG(MAX_RTC_RET_LOG),
|
|
.LOG_MAX_RX_TOKENS(LOG_MAX_RX_TOKENS),
|
|
.LOG_MAX_HMC_TOKENS(LOG_MAX_HMC_TOKENS),
|
|
.XIL_CNT_PIPELINED(XIL_CNT_PIPELINED),
|
//Debug
|
//Debug
|
.DBG_RX_TOKEN_MON(DBG_RX_TOKEN_MON)
|
.DBG_RX_TOKEN_MON(DBG_RX_TOKEN_MON),
|
|
.OPEN_RSP_MODE(OPEN_RSP_MODE)
|
) tx_link_I(
|
) tx_link_I(
|
|
|
//----------------------------------
|
//----------------------------------
|
//----SYSTEM INTERFACE
|
//----SYSTEM INTERFACE
|
//----------------------------------
|
//----------------------------------
|
| Line 253... |
Line 347... |
.phy_scrambled_data_out(phy_data_tx_link2phy),
|
.phy_scrambled_data_out(phy_data_tx_link2phy),
|
|
|
//----------------------------------
|
//----------------------------------
|
//----HMC IF
|
//----HMC IF
|
//----------------------------------
|
//----------------------------------
|
.hmc_LxRXPS(hmc_LxRXPS),
|
.LXRXPS(LXRXPS),
|
.hmc_LxTXPS(hmc_LxTXPS),
|
.LXTXPS(LXTXPS),
|
|
|
//----------------------------------
|
//----------------------------------
|
//----FROM HMC_TX_HTAX_LOGIC
|
//----FROM HMC_TX_HTAX_LOGIC
|
//----------------------------------
|
//----------------------------------
|
.d_in_data(tx_d_in_data),
|
.d_in_data(tx_d_in_data),
|
| Line 290... |
Line 384... |
.rf_sent_np(rf_cnt_np),
|
.rf_sent_np(rf_cnt_np),
|
.rf_sent_r(rf_cnt_r),
|
.rf_sent_r(rf_cnt_r),
|
.rf_run_length_bit_flip(rf_run_length_bit_flip),
|
.rf_run_length_bit_flip(rf_run_length_bit_flip),
|
.rf_error_abort_not_cleared(rf_error_abort_not_cleared),
|
.rf_error_abort_not_cleared(rf_error_abort_not_cleared),
|
//Status
|
//Status
|
.rf_hmc_is_in_sleep(rf_hmc_sleep),
|
.rf_hmc_received_init_null(rf_rx_init_status==3'b010),
|
.rf_hmc_received_init_null(rf_hmc_init_status[0]),
|
.rf_link_is_up(rf_link_up),
|
.rf_link_is_up(rf_link_status[1]),
|
|
.rf_descramblers_aligned(rf_all_descramblers_aligned),
|
.rf_descramblers_aligned(rf_all_descramblers_aligned),
|
.rf_tx_init_status(rf_tx_init_status),
|
.rf_tx_init_status(rf_tx_init_status),
|
.rf_hmc_tokens_av(rf_hmc_tokens_av),
|
.rf_hmc_tokens_av(rf_hmc_tokens_av),
|
.rf_rx_tokens_av(rf_rx_tokens_av),
|
.rf_rx_tokens_av(rf_rx_tokens_av),
|
//Control
|
//Control
|
.rf_hmc_sleep_requested(rf_set_hmc_sleep),
|
.rf_hmc_sleep_requested(rf_set_hmc_sleep),
|
.rf_hmc_init_cont_set(rf_hmc_init_cont_set),
|
.rf_warm_reset(rf_warm_reset),
|
.rf_scrambler_disable(rf_scrambler_disable),
|
.rf_scrambler_disable(rf_scrambler_disable),
|
.rf_rx_buffer_rtc(rf_rx_buffer_rtc),
|
.rf_rx_buffer_rtc(rf_rx_buffer_rtc),
|
.rf_first_cube_ID(rf_first_cube_ID),
|
|
.rf_irtry_to_send(rf_irtry_to_send),
|
.rf_irtry_to_send(rf_irtry_to_send),
|
.rf_run_length_enable(rf_run_length_enable),
|
.rf_run_length_enable(rf_run_length_enable)
|
//Debug
|
|
.rf_dbg_dont_send_tret(rf_dbg_dont_send_tret),
|
|
.rf_dbg_halt_on_error_abort(rf_dbg_halt_on_error_abort),
|
|
.rf_dbg_halt_on_tx_retry(rf_dbg_halt_on_tx_retry)
|
|
|
|
);
|
);
|
|
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
//-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX
|
//-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX-----RX
|
//----------------------------------------------------------------------
|
//----------------------------------------------------------------------
|
rx_link #(
|
rx_link #(
|
.LOG_FPW(LOG_FPW),
|
.LOG_FPW(LOG_FPW),
|
.FPW(FPW),
|
.FPW(FPW),
|
.LOG_NUM_LANES(LOG_NUM_LANES),
|
.LOG_NUM_LANES(LOG_NUM_LANES),
|
.HMC_RF_RWIDTH(HMC_RF_RWIDTH),
|
.RF_COUNTER_SIZE(RF_COUNTER_SIZE),
|
//Configure the functionality
|
//Configure the functionality
|
.LOG_MAX_RTC(LOG_MAX_RTC),
|
.XIL_CNT_PIPELINED(XIL_CNT_PIPELINED),
|
|
.LOG_MAX_RX_TOKENS(LOG_MAX_RX_TOKENS),
|
|
.MAX_RTC_RET_LOG(MAX_RTC_RET_LOG),
|
|
.RX_BIT_SLIP_CNT_LOG(RX_BIT_SLIP_CNT_LOG),
|
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
|
.CTRL_LANE_POLARITY(CTRL_LANE_POLARITY),
|
|
.DETECT_LANE_POLARITY(DETECT_LANE_POLARITY),
|
.CTRL_LANE_REVERSAL(CTRL_LANE_REVERSAL),
|
.CTRL_LANE_REVERSAL(CTRL_LANE_REVERSAL),
|
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
|
.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT),
|
|
.OPEN_RSP_MODE(OPEN_RSP_MODE),
|
|
.RX_RELAX_INIT_TIMING(RX_RELAX_INIT_TIMING)
|
) rx_link_I (
|
) rx_link_I (
|
|
|
//----------------------------------
|
//----------------------------------
|
//----SYSTEM INTERFACE
|
//----SYSTEM INTERFACE
|
//----------------------------------
|
//----------------------------------
|
| Line 337... |
Line 431... |
|
|
//----------------------------------
|
//----------------------------------
|
//----TO HMC PHY
|
//----TO HMC PHY
|
//----------------------------------
|
//----------------------------------
|
.phy_scrambled_data_in(phy_data_rx_phy2link),
|
.phy_scrambled_data_in(phy_data_rx_phy2link),
|
.init_bit_slip(phy_bit_slip),
|
.phy_bit_slip(phy_bit_slip),
|
|
.run_rx(phy_rx_ready),
|
|
|
//----------------------------------
|
//----------------------------------
|
//----FROM TO RX HTAX FIFO
|
//----FROM TO RX HTAX FIFO
|
//----------------------------------
|
//----------------------------------
|
.d_out_fifo_data(rx_d_in_data),
|
.d_out_fifo_data(rx_d_in_data),
|
.d_out_fifo_full(rx_full),
|
|
.d_out_fifo_a_full(rx_a_full),
|
.d_out_fifo_a_full(rx_a_full),
|
.d_out_fifo_shift_in(rx_shift_in),
|
.d_out_fifo_shift_in(rx_shift_in),
|
.d_out_fifo_ctrl(rx_d_in_ctrl),
|
.d_out_fifo_ctrl(rx_d_in_ctrl),
|
|
|
//----------------------------------
|
//----------------------------------
|
| Line 367... |
Line 461... |
//----------------------------------
|
//----------------------------------
|
//Monitoring 1-cycle set to increment
|
//Monitoring 1-cycle set to increment
|
.rf_cnt_poisoned(rf_cnt_poisoned),
|
.rf_cnt_poisoned(rf_cnt_poisoned),
|
.rf_cnt_rsp(rf_cnt_rsp_rcvd),
|
.rf_cnt_rsp(rf_cnt_rsp_rcvd),
|
//Status
|
//Status
|
.rf_link_status(rf_link_status),
|
.rf_link_up(rf_link_up),
|
.rf_hmc_init_status(rf_hmc_init_status),
|
.rf_rx_init_status(rf_rx_init_status),
|
.rf_hmc_sleep(rf_hmc_sleep),
|
.rf_hmc_sleep(~LXTXPS),
|
//Init Status
|
//Init Status
|
.rf_all_descramblers_aligned(rf_all_descramblers_aligned),
|
.rf_all_descramblers_aligned(rf_all_descramblers_aligned),
|
.rf_descrambler_aligned(rf_descrambler_aligned),
|
.rf_descrambler_aligned(rf_descrambler_aligned),
|
.rf_descrambler_part_aligned(rf_descrambler_part_aligned),
|
.rf_descrambler_part_aligned(rf_descrambler_part_aligned),
|
.rf_descramblers_locked(rf_descramblers_locked),
|
.rf_descramblers_locked(rf_descramblers_locked),
|
.rf_tx_sends_ts1(rf_tx_init_status[1] && !rf_tx_init_status[0]),
|
|
//Control
|
//Control
|
.rf_bit_slip_time(rf_bit_slip_time),
|
|
.rf_hmc_init_cont_set(rf_hmc_init_cont_set),
|
|
.rf_lane_polarity(rf_lane_polarity),
|
.rf_lane_polarity(rf_lane_polarity),
|
.rf_scrambler_disable(rf_scrambler_disable),
|
.rf_scrambler_disable(rf_scrambler_disable),
|
.rf_lane_reversal_detected(rf_lane_reversal_detected),
|
.rf_lane_reversal_detected(rf_lane_reversal_detected),
|
.rf_irtry_received_threshold(rf_irtry_received_threshold)
|
.rf_irtry_received_threshold(rf_irtry_received_threshold)
|
);
|
);
|
|
|
|
generate
|
|
if(SYNC_AXI4_IF==0) begin : async_axi4_rx_fifo
|
openhmc_async_fifo #(
|
openhmc_async_fifo #(
|
.DWIDTH(DWIDTH+(FPW*4)),
|
.DWIDTH(DWIDTH+(FPW*4)),
|
.ENTRIES(16)
|
.ENTRIES(16)
|
) fifo_rx_data(
|
) fifo_rx_data(
|
//System
|
//System
|
| Line 398... |
Line 491... |
.so_res_n(res_n_user),
|
.so_res_n(res_n_user),
|
|
|
//To RX LINK Logic
|
//To RX LINK Logic
|
.d_in({rx_d_in_ctrl,rx_d_in_data}),
|
.d_in({rx_d_in_ctrl,rx_d_in_data}),
|
.shift_in(rx_shift_in),
|
.shift_in(rx_shift_in),
|
.full(rx_full),
|
.full(),
|
.almost_full(rx_a_full),
|
.almost_full(rx_a_full),
|
|
|
//AXI-4 RX IF
|
//AXI-4 RX IF
|
.d_out({m_axis_rx_TUSER_temp,m_axis_rx_TDATA}),
|
.d_out({m_axis_rx_TUSER_temp,m_axis_rx_TDATA}),
|
.shift_out(m_axis_rx_TVALID && m_axis_rx_TREADY),
|
.shift_out(m_axis_rx_TVALID && m_axis_rx_TREADY),
|
.empty(m_axis_rx_TVALID_n),
|
.empty(m_axis_rx_TVALID_n),
|
.almost_empty()
|
.almost_empty()
|
|
|
);
|
);
|
|
end else begin : synchronous_axi4_rx_fifo
|
//----------------------------------------------------------------------
|
`ifdef XILINX
|
//---Register File---Register File---Register File---Register File---Reg
|
openhmc_sync_fifo_xilinx #(
|
//----------------------------------------------------------------------
|
.DWIDTH(DWIDTH+(FPW*4))
|
//Instantiate register file depending on the number of lanes
|
) fifo_rx_data_sync_xilinx(
|
generate
|
//System
|
if(NUM_LANES==8) begin : register_file_8x
|
|
openhmc_8x_rf openhmc_rf_I (
|
|
//system IF
|
|
.res_n(res_n_hmc),
|
|
.clk(clk_hmc),
|
.clk(clk_hmc),
|
|
.res_n(res_n_hmc),
|
|
|
//rf access
|
//To RX LINK Logic
|
.address(rf_address),
|
.d_in({rx_d_in_ctrl,rx_d_in_data}),
|
.read_data(rf_read_data),
|
.shift_in(rx_shift_in),
|
.invalid_address(rf_invalid_address),
|
.full(),
|
.access_complete(rf_access_complete),
|
.almost_full(rx_a_full),
|
.read_en(rf_read_en),
|
|
.write_en(rf_write_en),
|
|
.write_data(rf_write_data),
|
|
|
|
//status registers
|
|
.status_general_link_up_next(rf_link_status[1]),
|
|
.status_general_link_training_next(rf_link_status[0]),
|
|
.status_general_sleep_mode_next(rf_hmc_sleep),
|
|
.status_general_phy_ready_next(phy_ready),
|
|
.status_general_lanes_reversed_next(rf_lane_reversal_detected),
|
|
.status_general_hmc_tokens_remaining_next(rf_hmc_tokens_av),
|
|
.status_general_rx_tokens_remaining_next(rf_rx_tokens_av),
|
|
.status_general_lane_polarity_reversed_next(rf_lane_polarity),
|
|
|
|
//init status
|
|
.status_init_lane_descramblers_locked_next(rf_descramblers_locked),
|
|
.status_init_descrambler_part_aligned_next(rf_descrambler_part_aligned),
|
|
.status_init_descrambler_aligned_next(rf_descrambler_aligned),
|
|
.status_init_all_descramblers_aligned_next(rf_all_descramblers_aligned),
|
|
.status_init_tx_init_status_next(rf_tx_init_status),
|
|
.status_init_hmc_init_TS1_next(rf_hmc_init_status[0]),
|
|
|
|
//counters
|
|
.sent_np_cnt_next(rf_cnt_np),
|
|
.sent_p_cnt_next(rf_cnt_p),
|
|
.sent_r_cnt_next(rf_cnt_r),
|
|
.poisoned_packets_cnt_next(rf_cnt_poisoned),
|
|
.rcvd_rsp_cnt_next(rf_cnt_rsp_rcvd),
|
|
|
|
//Single bit counter
|
//AXI-4 RX IF
|
.tx_link_retries_count_countup(rf_cnt_retry),
|
.d_out({m_axis_rx_TUSER_temp,m_axis_rx_TDATA}),
|
.errors_on_rx_count_countup(rx2tx_error_abort_mode_cleared),
|
.shift_out(m_axis_rx_TVALID && m_axis_rx_TREADY),
|
.run_length_bit_flip_count_countup(rf_run_length_bit_flip),
|
.empty(m_axis_rx_TVALID_n),
|
.error_abort_not_cleared_count_countup(rf_error_abort_not_cleared),
|
.almost_empty()
|
|
);
|
|
`else
|
|
openhmc_sync_fifo_reg_based #(
|
|
.DWIDTH(DWIDTH+(FPW*4)),
|
|
.ENTRIES(4)
|
|
) fifo_rx_data_sync(
|
|
//System
|
|
.clk(clk_hmc),
|
|
.res_n(res_n_hmc),
|
|
|
//control
|
//To RX LINK Logic
|
.control_p_rst_n(P_RST_N),
|
.d_in({rx_d_in_ctrl,rx_d_in_data}),
|
.control_hmc_init_cont_set(rf_hmc_init_cont_set),
|
.shift_in(rx_shift_in),
|
.control_set_hmc_sleep(rf_set_hmc_sleep),
|
.full(),
|
.control_scrambler_disable(rf_scrambler_disable),
|
.almost_full(rx_a_full),
|
.control_run_length_enable(rf_run_length_enable),
|
|
.control_first_cube_ID(rf_first_cube_ID),
|
|
.control_debug_dont_send_tret(rf_dbg_dont_send_tret),
|
|
.control_debug_halt_on_error_abort(rf_dbg_halt_on_error_abort),
|
|
.control_debug_halt_on_tx_retry(rf_dbg_halt_on_tx_retry),
|
|
.control_rx_token_count(rf_rx_buffer_rtc),
|
|
.control_irtry_received_threshold(rf_irtry_received_threshold),
|
|
.control_irtry_to_send(rf_irtry_to_send),
|
|
.control_bit_slip_time(rf_bit_slip_time)
|
|
|
|
|
//AXI-4 RX IF
|
|
.d_out({m_axis_rx_TUSER_temp,m_axis_rx_TDATA}),
|
|
.shift_out(m_axis_rx_TVALID && m_axis_rx_TREADY),
|
|
.empty(m_axis_rx_TVALID_n),
|
|
.almost_empty()
|
);
|
);
|
end else begin : register_file_16x
|
`endif
|
openhmc_16x_rf openhmc_rf_I (
|
end
|
|
endgenerate
|
|
|
|
//----------------------------------------------------------------------
|
|
//---Register File---Register File---Register File---Register File---Reg
|
|
//----------------------------------------------------------------------
|
|
openhmc_rf #(
|
|
.NUM_LANES(NUM_LANES),
|
|
.XIL_CNT_PIPELINED(XIL_CNT_PIPELINED),
|
|
.LOG_MAX_RX_TOKENS(LOG_MAX_RX_TOKENS),
|
|
.LOG_MAX_HMC_TOKENS(LOG_MAX_HMC_TOKENS),
|
|
.RF_COUNTER_SIZE(RF_COUNTER_SIZE),
|
|
.HMC_RF_WWIDTH(HMC_RF_WWIDTH),
|
|
.HMC_RF_AWIDTH(HMC_RF_AWIDTH),
|
|
.HMC_RF_RWIDTH(HMC_RF_RWIDTH)
|
|
) openhmc_rf_I (
|
//system IF
|
//system IF
|
.res_n(res_n_hmc),
|
.res_n(res_n_hmc),
|
.clk(clk_hmc),
|
.clk(clk_hmc),
|
|
|
//rf access
|
//rf access
|
| Line 492... |
Line 574... |
.read_en(rf_read_en),
|
.read_en(rf_read_en),
|
.write_en(rf_write_en),
|
.write_en(rf_write_en),
|
.write_data(rf_write_data),
|
.write_data(rf_write_data),
|
|
|
//status registers
|
//status registers
|
.status_general_link_up_next(rf_link_status[1]),
|
.status_general_link_up_next(rf_link_up),
|
.status_general_link_training_next(rf_link_status[0]),
|
.status_general_link_training_next(~rf_link_up),
|
.status_general_sleep_mode_next(rf_hmc_sleep),
|
.status_general_sleep_mode_next(~LXTXPS),
|
.status_general_phy_ready_next(phy_ready),
|
.status_general_FERR_N_next(FERR_N),
|
|
.status_general_phy_tx_ready_next(phy_tx_ready),
|
|
.status_general_phy_rx_ready_next(phy_rx_ready),
|
.status_general_lanes_reversed_next(rf_lane_reversal_detected),
|
.status_general_lanes_reversed_next(rf_lane_reversal_detected),
|
.status_general_hmc_tokens_remaining_next(rf_hmc_tokens_av),
|
.status_general_hmc_tokens_remaining_next(rf_hmc_tokens_av),
|
.status_general_rx_tokens_remaining_next(rf_rx_tokens_av),
|
.status_general_rx_tokens_remaining_next(rf_rx_tokens_av),
|
.status_general_lane_polarity_reversed_next(rf_lane_polarity),
|
.status_general_lane_polarity_reversed_next(rf_lane_polarity),
|
|
|
//init status
|
//init status
|
.status_init_lane_descramblers_locked_next(rf_descramblers_locked),
|
.status_init_lane_descramblers_locked_next(rf_descramblers_locked),
|
.status_init_descrambler_part_aligned_next(rf_descrambler_part_aligned),
|
.status_init_descrambler_part_aligned_next(rf_descrambler_part_aligned),
|
.status_init_descrambler_aligned_next(rf_descrambler_aligned),
|
.status_init_descrambler_aligned_next(rf_descrambler_aligned),
|
.status_init_all_descramblers_aligned_next(rf_all_descramblers_aligned),
|
.status_init_all_descramblers_aligned_next(rf_all_descramblers_aligned),
|
.status_init_tx_init_status_next(rf_tx_init_status),
|
.status_init_rx_init_state_next(rf_rx_init_status),
|
.status_init_hmc_init_TS1_next(rf_hmc_init_status[0]),
|
.status_init_tx_init_state_next(rf_tx_init_status),
|
|
|
//counters
|
//counters
|
.sent_np_cnt_next(rf_cnt_np),
|
.sent_np_cnt_next(rf_cnt_np),
|
.sent_p_cnt_next(rf_cnt_p),
|
.sent_p_cnt_next(rf_cnt_p),
|
.sent_r_cnt_next(rf_cnt_r),
|
.sent_r_cnt_next(rf_cnt_r),
|
| Line 526... |
Line 610... |
|
|
//control
|
//control
|
.control_p_rst_n(P_RST_N),
|
.control_p_rst_n(P_RST_N),
|
.control_hmc_init_cont_set(rf_hmc_init_cont_set),
|
.control_hmc_init_cont_set(rf_hmc_init_cont_set),
|
.control_set_hmc_sleep(rf_set_hmc_sleep),
|
.control_set_hmc_sleep(rf_set_hmc_sleep),
|
.control_scrambler_disable(rf_scrambler_disable),
|
.control_warm_reset(rf_warm_reset),
|
|
.control_scrambler_disable(rf_scrambler_disable_temp),
|
.control_run_length_enable(rf_run_length_enable),
|
.control_run_length_enable(rf_run_length_enable),
|
.control_first_cube_ID(rf_first_cube_ID),
|
.control_rx_token_count(rf_rx_buffer_rtc_temp),
|
.control_debug_dont_send_tret(rf_dbg_dont_send_tret),
|
|
.control_debug_halt_on_error_abort(rf_dbg_halt_on_error_abort),
|
|
.control_debug_halt_on_tx_retry(rf_dbg_halt_on_tx_retry),
|
|
.control_rx_token_count(rf_rx_buffer_rtc),
|
|
.control_irtry_received_threshold(rf_irtry_received_threshold),
|
.control_irtry_received_threshold(rf_irtry_received_threshold),
|
.control_irtry_to_send(rf_irtry_to_send),
|
.control_irtry_to_send(rf_irtry_to_send)
|
.control_bit_slip_time(rf_bit_slip_time)
|
|
);
|
);
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
endmodule
|
|
|
`default_nettype wire
|
`default_nettype wire
|
|
|
No newline at end of file
|
No newline at end of file
|
