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https://opencores.org/ocsvn/openhmc/openhmc/trunk
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| Rev 11 |
Rev 15 |
| Line 80... |
Line 80... |
)
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)
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(
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(
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input wire clk,
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input wire clk,
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input wire res_n,
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input wire res_n,
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input wire bit_slip,
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input wire bit_slip,
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input wire can_lock,
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output reg locked,
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output reg locked,
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input wire [DWIDTH-1:0] data_in,
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input wire [DWIDTH-1:0] data_in,
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output reg [DWIDTH-1:0] data_out
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output reg [DWIDTH-1:0] data_out
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);
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);
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Line 101... |
end else begin
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end else begin
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assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
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assign lfsr_slipped = { lfsr_steps[DWIDTH-1][13:0], (lfsr_steps[DWIDTH-1][14] ^ lfsr_steps[DWIDTH-1][0])};
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end
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end
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endgenerate
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endgenerate
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`ifdef SIMULATION
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initial begin
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lfsr <= 15'h0;
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end
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`endif
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// SEQUENTIAL PROCESS
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// SEQUENTIAL PROCESS
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`ifdef ASYNC_RES
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk) begin `endif
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always @(posedge clk) begin `endif
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`ifdef RESET_ALL
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if (!res_n) begin
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if (!res_n) begin
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locked <= 1'b0;
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lfsr <= 15'h0;
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data_out <= {DWIDTH {1'b0}};
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data_out <= {DWIDTH {1'b0}};
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end else begin
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lfsr <= 15'h0;
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end else
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`endif
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begin
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data_out <= data_out_tmp;
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data_out <= data_out_tmp;
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if (!locked) begin
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if (!locked && |data_in) begin
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lfsr <= calculated_seed;
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lfsr <= calculated_seed;
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// Locked when the calculated seeds match
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if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
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locked <= 1'b1;
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end
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end else begin
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end else begin
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if (bit_slip) begin
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if (bit_slip) begin
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lfsr <= lfsr_slipped;
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lfsr <= lfsr_slipped;
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end else begin
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end else begin
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lfsr <= lfsr_steps[DWIDTH-1];
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lfsr <= lfsr_steps[DWIDTH-1];
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end
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end
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end
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end
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end
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end
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if(!res_n) begin
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locked <= 1'b0;
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end else begin
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if (!locked) begin
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if (calculated_seed == lfsr_steps[DWIDTH-1]) begin
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locked <= 1'b1;
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end
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end
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if(!can_lock) begin
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locked <= 1'b0;
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end
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end
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end // serial shift right with left input
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end // serial shift right with left input
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// SCRAMBLE
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// SCRAMBLE
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genvar j;
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genvar j;
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