| Line 59... |
Line 59... |
//----CONNECT
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//----CONNECT
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//----------------------------------
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//----------------------------------
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input wire [LANE_DWIDTH-1:0] scrambled_data_in,
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input wire [LANE_DWIDTH-1:0] scrambled_data_in,
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input wire bit_slip, //bit slip per lane
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input wire bit_slip, //bit slip per lane
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input wire lane_polarity,
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input wire lane_polarity,
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input wire can_lock,
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output wire [LANE_DWIDTH-1:0] descrambled_data_out,
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output wire [LANE_DWIDTH-1:0] descrambled_data_out,
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output wire descrambler_locked,
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output wire descrambler_locked,
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input wire descrambler_disable
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input wire descrambler_disable
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);
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);
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wire [LANE_DWIDTH-1:0] descrambled_data_out_tmp;
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wire [LANE_DWIDTH-1:0] descrambled_data_out_tmp;
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wire [LANE_DWIDTH-1:0] data_2_descrambler;
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wire [LANE_DWIDTH-1:0] data_2_descrambler;
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wire descrambler_locked_tmp;
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wire descrambler_locked_tmp;
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assign descrambler_locked = descrambler_disable ? 1'b1 : descrambler_locked_tmp;
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assign descrambler_locked = descrambler_disable ? can_lock : descrambler_locked_tmp;
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//=====================================================================================================
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//=====================================================================================================
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//-----------------------------------------------------------------------------------------------------
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//-----------------------------------------------------------------------------------------------------
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| Line 86... |
Line 87... |
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`ifdef ASYNC_RES
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk) begin `endif
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always @(posedge clk) begin `endif
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`ifdef RESET_ALL
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if(!res_n) begin
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if(!res_n) begin
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scrambled_data_in_reg <= {LANE_DWIDTH{1'b0}};
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scrambled_data_in_reg <= {LANE_DWIDTH{1'b0}};
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end
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end else
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else begin
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`endif
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begin
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scrambled_data_in_reg <= scrambled_data_in^{LANE_DWIDTH{lane_polarity}};
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scrambled_data_in_reg <= scrambled_data_in^{LANE_DWIDTH{lane_polarity}};
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end
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end
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end
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end
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assign data_2_descrambler = scrambled_data_in_reg;
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assign data_2_descrambler = scrambled_data_in_reg;
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| Line 118... |
Line 121... |
.DWIDTH(LANE_DWIDTH),
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.DWIDTH(LANE_DWIDTH),
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.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
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.BITSLIP_SHIFT_RIGHT(BITSLIP_SHIFT_RIGHT)
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) descrambler_I (
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) descrambler_I (
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.clk(clk),
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.clk(clk),
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.res_n(res_n),
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.res_n(res_n),
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.can_lock(can_lock),
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.bit_slip(bit_slip),
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.bit_slip(bit_slip),
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.locked(descrambler_locked_tmp),
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.locked(descrambler_locked_tmp),
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.data_in(data_2_descrambler),
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.data_in(data_2_descrambler),
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.data_out(descrambled_data_out_tmp)
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.data_out(descrambled_data_out_tmp)
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);
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);
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