| Line 130... |
Line 130... |
reg [FPW-1:0] crc_data_pipe_in_tail [1:0];
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reg [FPW-1:0] crc_data_pipe_in_tail [1:0];
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wire [128-1:0] crc_data_pipe_out_data_flit [FPW-1:0];
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wire [128-1:0] crc_data_pipe_out_data_flit [FPW-1:0];
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|
|
generate
|
generate
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for(f = 0; f < (FPW); f = f + 1) begin : assign_data_pipe_output
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for(f = 0; f < (FPW); f = f + 1) begin : assign_data_pipe_output
|
assign crc_data_pipe_out_data_flit[f] = crc_data_pipe_in_data[1][(f*128)+128-1:f*128];
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assign crc_data_pipe_out_data_flit[f] = crc_data_pipe_in_data[1][(f*128)+127:f*128];
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end
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end
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endgenerate
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endgenerate
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|
|
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reg [128-1:0] data_rdy_flit [FPW-1:0];
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reg [128-1:0] data_rdy_flit [FPW-1:0];
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| Line 245... |
Line 245... |
|
|
//Register input values to be used in CRC assignment logic after crc init stage
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//Register input values to be used in CRC assignment logic after crc init stage
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk) begin `endif
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always @(posedge clk) begin `endif
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|
|
|
//------------Data Propagation
|
|
`ifdef RESET_ALL
|
|
if(!res_n) d_in_data_dly <= {DWIDTH{1'b0}};
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else
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`endif
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d_in_data_dly <= d_in_data;
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//----------------------------
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|
|
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`ifdef RESET_ALL
|
if(!res_n) begin
|
if(!res_n) begin
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for(i_f=0;i_f<FPW;i_f=i_f+1)begin
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for(i_f=0;i_f<FPW;i_f=i_f+1)begin
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d_in_flit_lng_dly[i_f] <= 4'h0;
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d_in_flit_lng_dly[i_f] <= 4'h0;
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end
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end
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d_in_data_dly <= {DWIDTH{1'b0}};
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d_in_tail_dly <= {FPW{1'b0}};
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d_in_tail_dly <= {FPW{1'b0}};
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d_in_hdr_dly <= {FPW{1'b0}};
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d_in_hdr_dly <= {FPW{1'b0}};
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end else begin
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end else
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`endif
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begin
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for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
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d_in_flit_lng_dly[i_f] <= lng(d_in_flit[i_f]);
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d_in_flit_lng_dly[i_f] <= lng(d_in_flit[i_f]);
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end
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end
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d_in_data_dly <= d_in_data;
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d_in_tail_dly <= d_in_tail;
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d_in_tail_dly <= d_in_tail;
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d_in_hdr_dly <= d_in_hdr;
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d_in_hdr_dly <= d_in_hdr;
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end
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end
|
end
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end
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|
|
| Line 268... |
Line 278... |
//---------------------------------Inter CRC stage, CRC assignment Logic
|
//---------------------------------Inter CRC stage, CRC assignment Logic
|
//====================================================================
|
//====================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
//------------Data Propagation
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
`ifdef RESET_ALL
|
|
if(!res_n) crc_accu_in[i_f] <= {32{1'b0}};
|
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else
|
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`endif
|
|
crc_accu_in[i_f] <= crc_init_out[i_f];
|
|
end
|
|
//----------------------------
|
|
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
crc_accu_in[i_f] <= {32{1'b0}};
|
|
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
|
crc_accu_in_valid[i_f] <= {FPW{1'b0}};
|
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
|
crc_accu_in_tail[i_f] <= {FPW{1'b0}};
|
payload_remain[i_f] <= 4'h0;
|
payload_remain[i_f] <= 4'h0;
|
end
|
end
|
end else begin
|
end else begin
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
crc_accu_in[i_f] <= crc_init_out[i_f];
|
|
crc_accu_in_valid[i_f] <= 4'h0;
|
crc_accu_in_valid[i_f] <= 4'h0;
|
crc_accu_in_tail[i_f] <= 4'h0;
|
crc_accu_in_tail[i_f] <= 4'h0;
|
end
|
end
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
| Line 322... |
Line 342... |
//---------------------------------Constant propagation of the data pipeline
|
//---------------------------------Constant propagation of the data pipeline
|
//====================================================================
|
//====================================================================
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
|
|
|
//------------Data Propagation
|
|
`ifdef RESET_ALL
|
if(!res_n) begin
|
if(!res_n) begin
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
|
crc_data_pipe_in_data[i_c] <= {DWIDTH{1'b0}};
|
|
end
|
|
end else
|
|
`endif
|
|
begin
|
|
crc_data_pipe_in_data[0] <= d_in_data_dly;
|
|
crc_data_pipe_in_data[1] <= crc_data_pipe_in_data[0];
|
|
end
|
|
//----------------------------
|
|
|
|
`ifdef RESET_ALL
|
|
if(!res_n) begin
|
|
for(i_c=0;i_c<2;i_c=i_c+1)begin
|
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
|
crc_data_pipe_in_tail[i_c] <= {FPW{1'b0}};
|
end
|
end
|
|
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
target_crc_per_tail1[i_f] <= 3'h0;
|
target_crc_per_tail1[i_f] <= {LOG_FPW{1'b0}};
|
end
|
end
|
end else begin
|
end else
|
|
`endif
|
|
begin
|
|
|
//We keep the tails per FLIT so they are not part of the data pipe
|
//We keep the tails per FLIT so they are not part of the data pipe
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
for(i_f = 0; i_f < (FPW); i_f = i_f + 1) begin
|
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
|
target_crc_per_tail1[i_f] <= target_crc_per_tail[i_f];
|
end
|
end
|
|
|
//Set the first stage of the data pipeline
|
//Set the first stage of the data pipeline
|
crc_data_pipe_in_data[0] <= d_in_data_dly;
|
|
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
|
crc_data_pipe_in_tail[0] <= d_in_tail_dly;
|
|
|
//Data Pipeline propagation
|
//Data Pipeline propagation
|
for(i_c=0;i_c<(1);i_c=i_c+1)begin
|
crc_data_pipe_in_tail[1] <= crc_data_pipe_in_tail[0];
|
crc_data_pipe_in_data[i_c+1] <= crc_data_pipe_in_data[i_c];
|
|
crc_data_pipe_in_tail[i_c+1] <= crc_data_pipe_in_tail[i_c];
|
|
end
|
|
end
|
end
|
end
|
end
|
|
|
//====================================================================
|
//====================================================================
|
//---------------------------------At the end of the data pipeline get and add CRCs
|
//---------------------------------At the end of the data pipeline get and add CRCs
|
//====================================================================
|
//====================================================================
|
//Data Pipeline output stage to final FLIT reg
|
//Data Pipeline output stage to final FLIT reg
|
`ifdef ASYNC_RES
|
`ifdef ASYNC_RES
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk or negedge res_n) begin `else
|
always @(posedge clk) begin `endif
|
always @(posedge clk) begin `endif
|
if(!res_n) begin
|
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
`ifdef RESET_ALL
|
|
if(!res_n) begin
|
data_rdy_flit[i_f] <= {128{1'b0}};
|
data_rdy_flit[i_f] <= {128{1'b0}};
|
end
|
end else
|
|
`endif
|
end else begin
|
begin
|
|
|
for(i_f=0;i_f<FPW;i_f=i_f+1)begin
|
|
|
|
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
|
data_rdy_flit[i_f] <= crc_data_pipe_out_data_flit[i_f];
|
|
|
if(crc_data_pipe_in_tail[1][i_f])begin //Finally add the crc
|
if(crc_data_pipe_in_tail[1][i_f])begin //Finally add the crc
|
data_rdy_flit[i_f][128-1:128-32] <= crc_per_flit[target_crc_per_tail1[i_f]];
|
data_rdy_flit[i_f][128-1:128-32] <= crc_per_flit[target_crc_per_tail1[i_f]];
|
end
|
end
|
| Line 387... |
Line 418... |
generate
|
generate
|
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
|
for(f=0;f<FPW;f=f+1) begin : crc_init_gen
|
crc_128_init crc_init_I
|
crc_128_init crc_init_I
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
|
`ifdef RESET_ALL
|
.res_n(res_n),
|
.res_n(res_n),
|
|
`endif
|
.inData(d_in_flit[f]),
|
.inData(d_in_flit[f]),
|
.crc(crc_init_out[f])
|
.crc(crc_init_out[f])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
| Line 406... |
Line 439... |
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.res_n(res_n),
|
.res_n(res_n),
|
.tail(crc_accu_in_tail[f]),
|
.tail(crc_accu_in_tail[f]),
|
.d_in(crc_accu_in_combined[f]),
|
.d_in(crc_accu_in_combined[f]),
|
.valid(crc_accu_in_valid[f]),
|
|
.crc_out(crc_per_flit[f])
|
.crc_out(crc_per_flit[f])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
