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https://opencores.org/ocsvn/openhmc/openhmc/trunk
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| Rev 11 |
Rev 15 |
| Line 82... |
Line 82... |
//=====================================================================================================
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//=====================================================================================================
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wire [LANE_WIDTH-1:0] data_out_tmp;
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wire [LANE_WIDTH-1:0] data_out_tmp;
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wire [LANE_WIDTH-1:0] run_length_d_out;
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wire [LANE_WIDTH-1:0] run_length_d_out;
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reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
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reg [14:0] lfsr; // LINEAR FEEDBACK SHIFT REGISTER
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wire [14:0] lfsr_steps [LANE_WIDTH-1:0]; // LFSR values for serial time steps
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wire [14:0] lfsr_steps [LANE_WIDTH-1:0]; // LFSR values for serial time steps
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reg seed_set;
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// SEQUENTIAL PROCESS
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// SEQUENTIAL PROCESS
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`ifdef ASYNC_RES
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk or negedge res_n) begin `else
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always @(posedge clk) begin `endif
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always @(posedge clk) begin `endif
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`ifdef RESET_ALL
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if (!res_n) begin
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if (!res_n) begin
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seed_set <= 1'b0;
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lfsr[14:0] <= 15'h0;
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data_out <= {LANE_WIDTH {1'b0}};
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data_out <= {LANE_WIDTH {1'b0}};
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end
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end else
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else
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`endif
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begin
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begin
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if(!seed_set) begin
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lfsr[14:0] <= seed;
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seed_set <= 1'b1;
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end else begin
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if (disable_scrambler) begin
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lfsr[14:0] <= 15'h0;
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end else begin
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lfsr[14:0] <= lfsr_steps[LANE_WIDTH-1];
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end
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end
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data_out <= run_length_d_out;
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data_out <= run_length_d_out;
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end
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end
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end // serial shift right with left input
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if(!res_n) lfsr <= seed;
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else lfsr <= disable_scrambler ? {15{1'b0}} : lfsr_steps[LANE_WIDTH-1];
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end
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// SCRAMBLE
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// SCRAMBLE
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genvar j;
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genvar j;
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generate
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generate
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