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//
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//
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`ifndef AXI4_STREAM_IF_SV
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`ifndef AXI4_STREAM_IF_SV
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`define AXI4_STREAM_IF_SV
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`define AXI4_STREAM_IF_SV
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interface axi4_stream_if #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) (
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interface axi4_stream_if #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) ();
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input logic ACLK, //-- Clock (All signals sampled on the rising edge)
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input logic ARESET_N //-- Global Reset
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);
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//--
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//--
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//-- Interface signals
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//-- Interface signals
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//--
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//--
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logic ACLK; //-- Clock (All signals sampled on the rising edge)
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logic ARESET_N; //-- Global Reset
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logic TVALID; // Master valid
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logic TVALID; // Master valid
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logic TREADY; // Slave ready
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logic TREADY; // Slave ready
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logic [8*DATA_BYTES-1:0] TDATA; //-- Master data
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logic [8*DATA_BYTES-1:0] TDATA; //-- Master data
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logic [TUSER_WIDTH-1:0] TUSER; //-- Master sideband signals
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logic [TUSER_WIDTH-1:0] TUSER; //-- Master sideband signals
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logic [DATA_BYTES/16-1:0] DEBUG_VALIDS; //-- contains the HMC-VALID Flags
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logic [DATA_BYTES/16-1:0] DEBUG_VALIDS; //-- contains the HMC-VALID Flags
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logic [DATA_BYTES/16-1:0] DEBUG_HEADERS; //-- contains the HMC-HEADER Flags
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logic [DATA_BYTES/16-1:0] DEBUG_HEADERS; //-- contains the HMC-HEADER Flags
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logic [DATA_BYTES/16-1:0] DEBUG_TAILS; //-- contains the HMC-TAIL Flags
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logic [DATA_BYTES/16-1:0] DEBUG_TAILS; //-- contains the HMC-TAIL Flags
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//-- assigning the debug signals to TUSER
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//-- assigning the debug signals to TUSER
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assign DEBUG_VALIDS = TUSER[1*(DATA_BYTES /16)-1: (0* DATA_BYTES /16)];
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assign DEBUG_VALIDS = TUSER[1*(DATA_BYTES /16)-1: (0* DATA_BYTES /16)];
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assign DEBUG_HEADERS = TUSER[2*(DATA_BYTES /16)-1: (1* DATA_BYTES /16)];
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assign DEBUG_HEADERS = TUSER[2*(DATA_BYTES /16)-1: (1* DATA_BYTES /16)];
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assign DEBUG_TAILS = TUSER[3*(DATA_BYTES /16)-1: (2* DATA_BYTES /16)];
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assign DEBUG_TAILS = TUSER[3*(DATA_BYTES /16)-1: (2* DATA_BYTES /16)];
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//--
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//--
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//-- Interface Coverage
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//-- Interface Coverage
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//--
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//--
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covergroup axi4_cg @ (posedge ACLK);
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covergroup axi4_cg @ (posedge ACLK);
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// @(edge ACLK)
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// @(edge ACLK)
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// !ARESET_N |-> ARESET_N[->1];
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// !ARESET_N |-> ARESET_N[->1];
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//
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//
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//endproperty
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//endproperty
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chk_reset_tvalid : assert property (
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// chk_reset_tvalid : assert property (
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//-- TVALID must be inactive during Reset
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// //-- TVALID must be inactive during Reset
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@(posedge ACLK)
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// @(posedge ACLK)
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!ARESET_N |-> TVALID == 1'b0
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// !ARESET_N |-> TVALID == 1'b0
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);
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// );
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chk_valid_hold : assert property (
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chk_valid_hold : assert property (
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//-- if TVALID is set it must be active until TREADY
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//-- if TVALID is set it must be active until TREADY
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@(posedge ACLK) disable iff(!ARESET_N)
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@(posedge ACLK) disable iff(!ARESET_N)
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@(posedge ACLK ) disable iff (!ARESET_N)
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@(posedge ACLK ) disable iff (!ARESET_N)
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(TVALID && ( $countones(DEBUG_HEADERS) > $countones(DEBUG_TAILS) ))
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(TVALID && ( $countones(DEBUG_HEADERS) > $countones(DEBUG_TAILS) ))
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|=> (TVALID == 1) throughout ( $countones(DEBUG_HEADERS) < $countones(DEBUG_TAILS) )[->1]
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|=> (TVALID == 1) throughout ( $countones(DEBUG_HEADERS) < $countones(DEBUG_TAILS) )[->1]
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);
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);
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time clk_rise;
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time reset_rise;
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always @(posedge ACLK) begin
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if(ARESET_N == 0)
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clk_rise <= $time();
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end
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always @(posedge ARESET_N) begin
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reset_rise <= $time();
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end
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//TODO TODO ADD
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// check_sync_reset : assert property (
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// @(posedge ACLK)
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// $rose(ARESET_N) |=> (reset_rise == clk_rise)
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// );
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property data_hold_p;
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property data_hold_p;
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//-- if TVALID is set TDATA must not be changed until TREADY
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//-- if TVALID is set TDATA must not be changed until TREADY
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logic [8*DATA_BYTES-1:0] m_data;
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logic [8*DATA_BYTES-1:0] m_data;
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