| Line 60... |
Line 60... |
`include "register_file_model_8x.sv"
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`include "register_file_model_8x.sv"
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`endif
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`endif
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`include "hmc_packet.sv"
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`include "hmc_packet.sv"
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`include "hmc_req_packet.sv"
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`include "hmc_req_packet.sv"
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//`include "hmc_req_posted_packet.sv"
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`include "hmc_2_axi4_sequencer.sv"
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`include "hmc_2_axi4_sequencer.sv"
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`include "hmc_2_axi4_sequence.sv"
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`include "hmc_2_axi4_sequence.sv"
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`include "tag_handler.sv"
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`include "tag_handler.sv"
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`include "hmc_link_config.sv"
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`include "hmc_link_config.sv"
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`include "hmc_vseqr.sv"
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`include "vseqr.sv"
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`include "axi4_stream_hmc_monitor.sv"
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`include "axi4_stream_hmc_monitor.sv"
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`include "bfm_2_hmc_monitor.sv"
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`include "bfm_2_hmc_monitor.sv"
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`include "hmc_tb.sv"
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`include "hmc_tb.sv"
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| Line 81... |
Line 80... |
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//-- instantiate the interfaces
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//-- instantiate the interfaces
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axi4_stream_if #(
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axi4_stream_if #(
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.DATA_BYTES(`AXI4BYTES),
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.DATA_BYTES(`AXI4BYTES),
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.TUSER_WIDTH(`AXI4BYTES)
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.TUSER_WIDTH(`AXI4BYTES)
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) axi4_hmc_req_if(
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) axi4_hmc_req_if();
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.ACLK(clk_user),
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.ARESET_N(res_n)
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);
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axi4_stream_if #(
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axi4_stream_if #(
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.DATA_BYTES(`AXI4BYTES),
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.DATA_BYTES(`AXI4BYTES),
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.TUSER_WIDTH(`AXI4BYTES)
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.TUSER_WIDTH(`AXI4BYTES)
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) axi4_hmc_rsp_if(
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) axi4_hmc_rsp_if();
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.ACLK(clk_user),
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.ARESET_N(res_n)
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);
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cag_rgm_rfs_if #(
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cag_rgm_rfs_if #(
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.ADDR_WIDTH(`RFS_HMC_CONTROLLER_RF_AWIDTH),
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.ADDR_WIDTH(`RFS_OPENHMC_RF_AWIDTH),
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.READ_DATA_WIDTH(`RFS_HMC_CONTROLLER_RF_RWIDTH),
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.READ_DATA_WIDTH(`RFS_OPENHMC_RF_RWIDTH),
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.WRITE_DATA_WIDTH(`RFS_HMC_CONTROLLER_RF_WWIDTH)
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.WRITE_DATA_WIDTH(`RFS_OPENHMC_RF_WWIDTH)
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) rfs_hmc_if();
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) rfs_hmc_if();
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dut dut_I (
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dut dut_I (
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.clk_user(clk_user),
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.clk_user(clk_user),
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.clk_hmc_refclk(clk_hmc_refclk),
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.clk_hmc_refclk(clk_hmc_refclk),
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| Line 120... |
Line 113... |
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//-- connect the BFM monitors with the Module UVC BFM to HMC Packet monitors
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//-- connect the BFM monitors with the Module UVC BFM to HMC Packet monitors
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uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_req_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_rsp_pkt[0]);
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uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_req_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_rsp_pkt[0]);
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uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_rsp_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_req_pkt[0]);
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uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_rsp_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_req_pkt[0]);
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//uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_req_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_req_pkt_err_cov[0]);
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//uvm_config_db#(pkt_analysis_port#())::set(null,"uvm_test_top.hmc_tb0.hmc_module.hmc_rsp_mon","mb_pkt",dut_I.hmc_bfm0.hmc_flit_top.mb_rsp_pkt_err_cov[0]);
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run_test();
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run_test();
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end
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end
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initial begin
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initial begin
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clk_user <= 1'b1;
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clk_user <= 1'b1;
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clk_hmc_refclk <= 1'b1;
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clk_hmc_refclk <= 1'b1;
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res_n <= 1'b0;
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res_n <= 1'b0;
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#1000ns
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#500ns;
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@(posedge clk_user) res_n <= 1'b1;
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@(posedge clk_user) res_n <= 1'b1;
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end
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end
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//-- Generate the user clock
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//-- Generate the user clock
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always begin
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always begin
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| Line 165... |
Line 155... |
#3.2ns clk_user = !clk_user;
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#3.2ns clk_user = !clk_user;
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end
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end
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endcase
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endcase
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end
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end
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//-- 125 MHz
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//-- 125 MHz HMC/Transceiver refclock
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always #4ns clk_hmc_refclk <= ~clk_hmc_refclk;
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always #4ns clk_hmc_refclk <= ~clk_hmc_refclk;
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endmodule : tb_top
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endmodule : tb_top
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No newline at end of file
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No newline at end of file
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