Subversion Repositories openjtag-project

# -------------------------------------------------------------------------- #

#

# Copyright (C) 1991-2010 Altera Corporation

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, Altera MegaCore Function License

# Agreement, or other applicable license agreement, including,

# without limitation, that your use is for the sole purpose of

# programming logic devices manufactured by Altera and sold by

# Altera or its authorized distributors.  Please refer to the

# applicable agreement for further details.

#

# -------------------------------------------------------------------------- #

#

# Quartus II

# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition

# Date created = 15:56:20  June 02, 2010

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               Open_JTAG_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "MAX II"

set_global_assignment -name DEVICE EPM570T100C5

set_global_assignment -name TOP_LEVEL_ENTITY Open_JTAG

set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:56:20  JUNE 02, 2010"

set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"

set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga

set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP

set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100

set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V

set_global_assignment -name VECTOR_WAVEFORM_FILE Open_JTAG.vwf

set_global_assignment -name VHDL_FILE tap_sm.vhd

set_global_assignment -name VHDL_FILE clock_mux.vhd

set_global_assignment -name VHDL_FILE serializer.vhd

set_global_assignment -name BDF_FILE Open_JTAG.bdf

set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"

set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"