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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 17 $
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Register B/W and addresses
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// Register B/W and addresses
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parameter CPU_ID_LO = (8'h00 | 8'h00);
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parameter CPU_ID_LO = (8'h00 | 8'h00);
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parameter CPU_ID_HI = (8'h00 | 8'h01);
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parameter CPU_ID_HI = (8'h00 | 8'h01);
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Line 76... |
// If the auto synchronization mode is set, then the communication speed
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// If the auto synchronization mode is set, then the communication speed
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// is configured by the testbench.
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// is configured by the testbench.
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// If not, the values from the openMSP430.inc file are taken over.
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// If not, the values from the openMSP430.inc file are taken over.
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`ifdef DBG_UART_AUTO_SYNC
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`ifdef DBG_UART_AUTO_SYNC
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parameter UART_BAUD = 4000000;
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parameter UART_BAUD = 4000000;
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parameter UART_CNT = ((20000000/UART_BAUD)-1);
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integer UART_PERIOD = 1000000000/UART_BAUD;
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`else
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`else
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parameter UART_CNT = `DBG_UART_CNT;
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integer UART_PERIOD = `DBG_UART_CNT;
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`endif
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`endif
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Receive UART frame from CPU Debug interface (8N1)
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// Receive UART frame from CPU Debug interface (8N1)
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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task dbg_uart_rx;
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task dbg_uart_rx;
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output [7:0] dbg_rxbuf;
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output [7:0] dbg_rxbuf;
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reg [7:0] dbg_rxbuf;
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reg [7:0] dbg_rxbuf;
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reg [7:0] rxbuf;
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reg [7:0] rxbuf;
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integer rxcnt;
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integer rxcnt;
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begin
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begin
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#(1);
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dbg_uart_rx_busy = 1'b1;
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@(negedge dbg_uart_txd);
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@(negedge dbg_uart_txd);
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dbg_rxbuf = 0;
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dbg_rxbuf = 0;
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rxbuf = 0;
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rxbuf = 0;
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repeat((UART_CNT+1)/2) @(posedge mclk);
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#(3*UART_PERIOD/2);
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for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
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for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
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begin
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begin
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repeat(UART_CNT+1) @(posedge mclk);
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rxbuf = {dbg_uart_txd, rxbuf[7:1]};
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rxbuf = {dbg_uart_txd, rxbuf[7:1]};
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#(UART_PERIOD);
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end
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end
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dbg_rxbuf = rxbuf;
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dbg_rxbuf = rxbuf;
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dbg_uart_rx_busy = 1'b0;
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end
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end
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endtask
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endtask
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task dbg_uart_rx16;
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task dbg_uart_rx16;
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Line 140... |
input [7:0] txbuf;
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input [7:0] txbuf;
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reg [9:0] txbuf_full;
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reg [9:0] txbuf_full;
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integer txcnt;
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integer txcnt;
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begin
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begin
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dbg_uart_rxd = 1'b1;
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#(1);
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dbg_uart_tx_busy = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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txbuf_full = {1'b1, txbuf, 1'b0};
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txbuf_full = {1'b1, txbuf, 1'b0};
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for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
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for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
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begin
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begin
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repeat(UART_CNT+1) @(posedge mclk);
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#(UART_PERIOD);
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dbg_uart_rxd = txbuf_full[txcnt];
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dbg_uart_rxd_pre = txbuf_full[txcnt];
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end
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end
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dbg_uart_tx_busy = 1'b0;
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end
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end
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endtask
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endtask
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task dbg_uart_tx16;
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task dbg_uart_tx16;
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input [15:0] txbuf;
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input [15:0] txbuf;
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Line 162... |
dbg_uart_tx(txbuf[7:0]);
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dbg_uart_tx(txbuf[7:0]);
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dbg_uart_tx(txbuf[15:8]);
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dbg_uart_tx(txbuf[15:8]);
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end
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end
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endtask
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endtask
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always @(posedge mclk or posedge dbg_rst)
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if (dbg_rst)
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begin
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dbg_uart_rxd_sel <= 1'b0;
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dbg_uart_rxd_dly <= 1'b1;
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end
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else if (dbg_en)
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begin
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dbg_uart_rxd_sel <= dbg_uart_rxd_meta ? $random : 1'b0;
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dbg_uart_rxd_dly <= dbg_uart_rxd_pre;
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end
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assign dbg_uart_rxd = dbg_uart_rxd_sel ? dbg_uart_rxd_dly : dbg_uart_rxd_pre;
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Write to Debug register
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// Write to Debug register
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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task dbg_uart_wr;
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task dbg_uart_wr;
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Line 213... |
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dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
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dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
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end
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end
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endtask
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endtask
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No newline at end of file
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No newline at end of file
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//----------------------------------------------------------------------------
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// Send synchronization frame
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//----------------------------------------------------------------------------
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task dbg_uart_sync;
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begin
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dbg_uart_tx(DBG_SYNC);
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repeat(10) @(posedge mclk);
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end
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endtask
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No newline at end of file
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No newline at end of file
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