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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [dbg_uart_tasks.v] - Diff between revs 134 and 154

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Rev 134 Rev 154
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 134 $
// $Rev: 154 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
// Register B/W and addresses
// Register B/W and addresses
parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
Line 59... Line 59...
parameter           BRK2_ADDR1   =  (8'h00 | 8'h13);
parameter           BRK2_ADDR1   =  (8'h00 | 8'h13);
parameter           BRK3_CTL     =  (8'h40 | 8'h14);
parameter           BRK3_CTL     =  (8'h40 | 8'h14);
parameter           BRK3_STAT    =  (8'h40 | 8'h15);
parameter           BRK3_STAT    =  (8'h40 | 8'h15);
parameter           BRK3_ADDR0   =  (8'h00 | 8'h16);
parameter           BRK3_ADDR0   =  (8'h00 | 8'h16);
parameter           BRK3_ADDR1   =  (8'h00 | 8'h17);
parameter           BRK3_ADDR1   =  (8'h00 | 8'h17);
 
parameter           CPU_NR       =  (8'h00 | 8'h18);
 
 
// Read / Write commands
// Read / Write commands
parameter           DBG_WR       =   8'h80;
parameter           DBG_WR       =   8'h80;
parameter           DBG_RD       =   8'h00;
parameter           DBG_RD       =   8'h00;
 
 

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