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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [dbg_uart_tasks.v] - Diff between revs 2 and 17

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Rev 2 Rev 17
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
// $Rev: 17 $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
 
//----------------------------------------------------------------------------
 
 
// Register B/W and addresses
// Register B/W and addresses
parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
parameter           CPU_ID_LO    =  (8'h00 | 8'h00);
parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
parameter           CPU_ID_HI    =  (8'h00 | 8'h01);
parameter           CPU_CTL      =  (8'h40 | 8'h02);
parameter           CPU_CTL      =  (8'h40 | 8'h02);

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