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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [ram.v] - Diff between revs 17 and 23

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 17 $
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
 
`include "openMSP430_defines.v"
 
 
module ram (
module ram (
 
 
// OUTPUTs
// OUTPUTs
    ram_dout,                      // RAM data output
    ram_dout,                      // RAM data output

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