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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $Rev: 72 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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// $LastChangedDate: 2010-08-01 20:54:37 +0200 (Sun, 01 Aug 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module ram (
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module ram (
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ram_wen // RAM write enable (low active)
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ram_wen // RAM write enable (low active)
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);
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);
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// PARAMETERs
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// PARAMETERs
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//============
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//============
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parameter ADDR_MSB = 6;
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parameter ADDR_MSB = 6; // MSB of the address bus
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parameter MEM_SIZE = 256; // Memory size in bytes
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// OUTPUTs
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// OUTPUTs
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//============
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//============
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output [15:0] ram_dout; // RAM data output
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output [15:0] ram_dout; // RAM data output
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// RAM
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// RAM
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//============
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//============
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reg [15:0] mem [(1<<(ADDR_MSB+1))-1:0];
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reg [15:0] mem [(MEM_SIZE/2)-1:0];
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reg [ADDR_MSB:0] ram_addr_reg;
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reg [ADDR_MSB:0] ram_addr_reg;
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wire [15:0] mem_val = mem[ram_addr];
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wire [15:0] mem_val = mem[ram_addr];
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always @(posedge ram_clk)
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always @(posedge ram_clk)
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if (~ram_cen)
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if (~ram_cen & ram_addr<(MEM_SIZE/2))
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begin
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begin
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if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
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if (ram_wen==2'b00) mem[ram_addr] <= ram_din;
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else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
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else if (ram_wen==2'b01) mem[ram_addr] <= {ram_din[15:8], mem_val[7:0]};
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else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
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else if (ram_wen==2'b10) mem[ram_addr] <= {mem_val[15:8], ram_din[7:0]};
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ram_addr_reg <= ram_addr;
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ram_addr_reg <= ram_addr;
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