URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [ram.v] - Diff between revs 72 and 84

Rev 72	Rev 84
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 72 $`	`// $Rev: 84 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2010-08-01 20:54:37 +0200 (Sun, 01 Aug 2010) $`	`// $LastChangedDate: 2011-01-23 21:00:36 +0100 (Sun, 23 Jan 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "timescale.v"	`include "timescale.v"
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module ram (`	`module ram (`
Line 70...	Line 70...


`// RAM`	`// RAM`
`//============`	`//============`

`reg [15:0] mem [(MEM_SIZE/2)-1:0];`	`reg [15:0] mem [0:(MEM_SIZE/2)-1];`
`reg [ADDR_MSB:0] ram_addr_reg;`	`reg [ADDR_MSB:0] ram_addr_reg;`

`wire [15:0] mem_val = mem[ram_addr];`	`wire [15:0] mem_val = mem[ram_addr];`