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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Diff between revs 2 and 17

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
// $Rev: 17 $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
 
//----------------------------------------------------------------------------
 
 
// CPU registers
// CPU registers
//======================
//======================
 
 
wire       [15:0] r0    = dut.execution_unit_0.register_file_0.r0;
wire       [15:0] r0    = dut.execution_unit_0.register_file_0.r0;

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