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Line 30... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 17 $
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// $Rev: 33 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
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// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// CPU registers
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// CPU registers
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//======================
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//======================
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Line 59... |
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// RAM cells
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// RAM cells
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//======================
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//======================
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wire [15:0] mem200 = ram_0.mem[0];
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wire [15:0] mem200 = dmem_0.mem[0];
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wire [15:0] mem202 = ram_0.mem[1];
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wire [15:0] mem202 = dmem_0.mem[1];
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wire [15:0] mem204 = ram_0.mem[2];
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wire [15:0] mem204 = dmem_0.mem[2];
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wire [15:0] mem206 = ram_0.mem[3];
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wire [15:0] mem206 = dmem_0.mem[3];
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wire [15:0] mem208 = ram_0.mem[4];
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wire [15:0] mem208 = dmem_0.mem[4];
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wire [15:0] mem20A = ram_0.mem[5];
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wire [15:0] mem20A = dmem_0.mem[5];
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wire [15:0] mem20C = ram_0.mem[6];
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wire [15:0] mem20C = dmem_0.mem[6];
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wire [15:0] mem20E = ram_0.mem[7];
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wire [15:0] mem20E = dmem_0.mem[7];
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wire [15:0] mem210 = ram_0.mem[8];
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wire [15:0] mem210 = dmem_0.mem[8];
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wire [15:0] mem212 = ram_0.mem[9];
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wire [15:0] mem212 = dmem_0.mem[9];
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wire [15:0] mem214 = ram_0.mem[10];
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wire [15:0] mem214 = dmem_0.mem[10];
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wire [15:0] mem216 = ram_0.mem[11];
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wire [15:0] mem216 = dmem_0.mem[11];
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wire [15:0] mem218 = ram_0.mem[12];
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wire [15:0] mem218 = dmem_0.mem[12];
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wire [15:0] mem21A = ram_0.mem[13];
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wire [15:0] mem21A = dmem_0.mem[13];
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wire [15:0] mem21C = ram_0.mem[14];
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wire [15:0] mem21C = dmem_0.mem[14];
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wire [15:0] mem21E = ram_0.mem[15];
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wire [15:0] mem21E = dmem_0.mem[15];
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wire [15:0] mem220 = ram_0.mem[16];
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wire [15:0] mem220 = dmem_0.mem[16];
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wire [15:0] mem222 = ram_0.mem[17];
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wire [15:0] mem222 = dmem_0.mem[17];
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wire [15:0] mem224 = ram_0.mem[18];
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wire [15:0] mem224 = dmem_0.mem[18];
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wire [15:0] mem226 = ram_0.mem[19];
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wire [15:0] mem226 = dmem_0.mem[19];
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wire [15:0] mem228 = ram_0.mem[20];
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wire [15:0] mem228 = dmem_0.mem[20];
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wire [15:0] mem22A = ram_0.mem[21];
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wire [15:0] mem22A = dmem_0.mem[21];
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wire [15:0] mem22C = ram_0.mem[22];
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wire [15:0] mem22C = dmem_0.mem[22];
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wire [15:0] mem22E = ram_0.mem[23];
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wire [15:0] mem22E = dmem_0.mem[23];
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wire [15:0] mem230 = ram_0.mem[24];
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wire [15:0] mem230 = dmem_0.mem[24];
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wire [15:0] mem232 = ram_0.mem[25];
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wire [15:0] mem232 = dmem_0.mem[25];
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wire [15:0] mem234 = ram_0.mem[26];
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wire [15:0] mem234 = dmem_0.mem[26];
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wire [15:0] mem236 = ram_0.mem[27];
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wire [15:0] mem236 = dmem_0.mem[27];
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wire [15:0] mem238 = ram_0.mem[28];
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wire [15:0] mem238 = dmem_0.mem[28];
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wire [15:0] mem23A = ram_0.mem[29];
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wire [15:0] mem23A = dmem_0.mem[29];
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wire [15:0] mem23C = ram_0.mem[30];
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wire [15:0] mem23C = dmem_0.mem[30];
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wire [15:0] mem23E = ram_0.mem[31];
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wire [15:0] mem23E = dmem_0.mem[31];
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wire [15:0] mem240 = ram_0.mem[32];
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wire [15:0] mem240 = dmem_0.mem[32];
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wire [15:0] mem242 = ram_0.mem[33];
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wire [15:0] mem242 = dmem_0.mem[33];
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wire [15:0] mem244 = ram_0.mem[34];
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wire [15:0] mem244 = dmem_0.mem[34];
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wire [15:0] mem246 = ram_0.mem[35];
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wire [15:0] mem246 = dmem_0.mem[35];
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wire [15:0] mem248 = ram_0.mem[36];
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wire [15:0] mem248 = dmem_0.mem[36];
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wire [15:0] mem24A = ram_0.mem[37];
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wire [15:0] mem24A = dmem_0.mem[37];
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wire [15:0] mem24C = ram_0.mem[38];
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wire [15:0] mem24C = dmem_0.mem[38];
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wire [15:0] mem24E = ram_0.mem[39];
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wire [15:0] mem24E = dmem_0.mem[39];
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wire [15:0] mem250 = ram_0.mem[40];
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wire [15:0] mem250 = dmem_0.mem[40];
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wire [15:0] mem252 = ram_0.mem[41];
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wire [15:0] mem252 = dmem_0.mem[41];
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wire [15:0] mem254 = ram_0.mem[42];
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wire [15:0] mem254 = dmem_0.mem[42];
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wire [15:0] mem256 = ram_0.mem[43];
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wire [15:0] mem256 = dmem_0.mem[43];
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wire [15:0] mem258 = ram_0.mem[44];
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wire [15:0] mem258 = dmem_0.mem[44];
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wire [15:0] mem25A = ram_0.mem[45];
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wire [15:0] mem25A = dmem_0.mem[45];
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wire [15:0] mem25C = ram_0.mem[46];
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wire [15:0] mem25C = dmem_0.mem[46];
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wire [15:0] mem25E = ram_0.mem[47];
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wire [15:0] mem25E = dmem_0.mem[47];
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wire [15:0] mem260 = ram_0.mem[48];
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wire [15:0] mem260 = dmem_0.mem[48];
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wire [15:0] mem262 = ram_0.mem[49];
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wire [15:0] mem262 = dmem_0.mem[49];
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wire [15:0] mem264 = ram_0.mem[50];
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wire [15:0] mem264 = dmem_0.mem[50];
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wire [15:0] mem266 = ram_0.mem[51];
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wire [15:0] mem266 = dmem_0.mem[51];
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wire [15:0] mem268 = ram_0.mem[52];
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wire [15:0] mem268 = dmem_0.mem[52];
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wire [15:0] mem26A = ram_0.mem[53];
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wire [15:0] mem26A = dmem_0.mem[53];
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wire [15:0] mem26C = ram_0.mem[54];
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wire [15:0] mem26C = dmem_0.mem[54];
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wire [15:0] mem26E = ram_0.mem[55];
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wire [15:0] mem26E = dmem_0.mem[55];
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wire [15:0] mem270 = ram_0.mem[56];
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wire [15:0] mem270 = dmem_0.mem[56];
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wire [15:0] mem272 = ram_0.mem[57];
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wire [15:0] mem272 = dmem_0.mem[57];
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wire [15:0] mem274 = ram_0.mem[58];
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wire [15:0] mem274 = dmem_0.mem[58];
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wire [15:0] mem276 = ram_0.mem[59];
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wire [15:0] mem276 = dmem_0.mem[59];
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wire [15:0] mem278 = ram_0.mem[60];
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wire [15:0] mem278 = dmem_0.mem[60];
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wire [15:0] mem27A = ram_0.mem[61];
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wire [15:0] mem27A = dmem_0.mem[61];
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wire [15:0] mem27C = ram_0.mem[62];
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wire [15:0] mem27C = dmem_0.mem[62];
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wire [15:0] mem27E = ram_0.mem[63];
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wire [15:0] mem27E = dmem_0.mem[63];
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wire [15:0] mem280 = ram_0.mem[64];
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wire [15:0] mem280 = dmem_0.mem[64];
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// Interrupt vectors
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// Interrupt vectors
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//======================
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//======================
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wire [15:0] irq_vect_15 = rom_0.mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector
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wire [15:0] irq_vect_15 = pmem_0.mem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector
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wire [15:0] irq_vect_14 = rom_0.mem[(1<<(`ROM_MSB+1))-2]; // NMI
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wire [15:0] irq_vect_14 = pmem_0.mem[(1<<(`PMEM_MSB+1))-2]; // NMI
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wire [15:0] irq_vect_13 = rom_0.mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13
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wire [15:0] irq_vect_13 = pmem_0.mem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13
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wire [15:0] irq_vect_12 = rom_0.mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12
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wire [15:0] irq_vect_12 = pmem_0.mem[(1<<(`PMEM_MSB+1))-4]; // IRQ 12
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wire [15:0] irq_vect_11 = rom_0.mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11
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wire [15:0] irq_vect_11 = pmem_0.mem[(1<<(`PMEM_MSB+1))-5]; // IRQ 11
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wire [15:0] irq_vect_10 = rom_0.mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10
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wire [15:0] irq_vect_10 = pmem_0.mem[(1<<(`PMEM_MSB+1))-6]; // IRQ 10
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wire [15:0] irq_vect_09 = rom_0.mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9
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wire [15:0] irq_vect_09 = pmem_0.mem[(1<<(`PMEM_MSB+1))-7]; // IRQ 9
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wire [15:0] irq_vect_08 = rom_0.mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8
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wire [15:0] irq_vect_08 = pmem_0.mem[(1<<(`PMEM_MSB+1))-8]; // IRQ 8
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wire [15:0] irq_vect_07 = rom_0.mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7
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wire [15:0] irq_vect_07 = pmem_0.mem[(1<<(`PMEM_MSB+1))-9]; // IRQ 7
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wire [15:0] irq_vect_06 = rom_0.mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6
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wire [15:0] irq_vect_06 = pmem_0.mem[(1<<(`PMEM_MSB+1))-10]; // IRQ 6
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wire [15:0] irq_vect_05 = rom_0.mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5
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wire [15:0] irq_vect_05 = pmem_0.mem[(1<<(`PMEM_MSB+1))-11]; // IRQ 5
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wire [15:0] irq_vect_04 = rom_0.mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4
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wire [15:0] irq_vect_04 = pmem_0.mem[(1<<(`PMEM_MSB+1))-12]; // IRQ 4
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wire [15:0] irq_vect_03 = rom_0.mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3
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wire [15:0] irq_vect_03 = pmem_0.mem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
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wire [15:0] irq_vect_02 = rom_0.mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_02 = pmem_0.mem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
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wire [15:0] irq_vect_01 = rom_0.mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_01 = pmem_0.mem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
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wire [15:0] irq_vect_00 = rom_0.mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0
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wire [15:0] irq_vect_00 = pmem_0.mem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
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No newline at end of file
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No newline at end of file
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