URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Diff between revs 33 and 76

Rev 33	Rev 76
Line 30...	Line 30...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 33 $`	`// $Rev: 76 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $`	`// $LastChangedDate: 2010-11-18 22:01:37 +0100 (Thu, 18 Nov 2010) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`

`// CPU registers`	`// CPU registers`
`//======================`	`//======================`

Line 123...	Line 123...
`wire [15:0] mem276 = dmem_0.mem[59];`	`wire [15:0] mem276 = dmem_0.mem[59];`
`wire [15:0] mem278 = dmem_0.mem[60];`	`wire [15:0] mem278 = dmem_0.mem[60];`
`wire [15:0] mem27A = dmem_0.mem[61];`	`wire [15:0] mem27A = dmem_0.mem[61];`
`wire [15:0] mem27C = dmem_0.mem[62];`	`wire [15:0] mem27C = dmem_0.mem[62];`
`wire [15:0] mem27E = dmem_0.mem[63];`	`wire [15:0] mem27E = dmem_0.mem[63];`
`wire [15:0] mem280 = dmem_0.mem[64];`


`// Interrupt vectors`	`// Interrupt vectors`
`//======================`	`//======================`