URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 76 |
Rev 94 |
| Line 30... |
Line 30... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 76 $
|
// $Rev: 94 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2010-11-18 22:01:37 +0100 (Thu, 18 Nov 2010) $
|
// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
|
|
// CPU registers
|
// CPU registers
|
//======================
|
//======================
|
|
|
| Line 145... |
Line 145... |
wire [15:0] irq_vect_03 = pmem_0.mem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
|
wire [15:0] irq_vect_03 = pmem_0.mem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
|
wire [15:0] irq_vect_02 = pmem_0.mem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
|
wire [15:0] irq_vect_02 = pmem_0.mem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
|
wire [15:0] irq_vect_01 = pmem_0.mem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
|
wire [15:0] irq_vect_01 = pmem_0.mem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
|
wire [15:0] irq_vect_00 = pmem_0.mem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
|
wire [15:0] irq_vect_00 = pmem_0.mem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0
|
|
|
No newline at end of file
|
No newline at end of file
|
|
// Interrupt detection
|
|
wire nmi_detect = dut.frontend_0.inst_nmi;
|
|
wire irq_detect = dut.frontend_0.irq_detect;
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.