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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [tb_openMSP430.v] - Diff between revs 99 and 103

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 99 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-02-28 21:26:17 +0100 (Mon, 28 Feb 2011) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
 
`ifdef OMSP_NO_INCLUDE
 
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
`endif
 
 
module  tb_openMSP430;
module  tb_openMSP430;
 
 
//
//
// Wire & Register definition
// Wire & Register definition

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