| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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| Line 63... |
Line 63... |
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// Peripherals interface
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// Peripherals interface
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wire [7:0] per_addr;
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wire [7:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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wire [1:0] per_wen;
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wire [1:0] per_we;
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wire per_en;
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wire per_en;
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// Digital I/O
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// Digital I/O
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wire irq_port1;
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wire irq_port1;
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wire irq_port2;
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wire irq_port2;
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| Line 130... |
Line 130... |
wire puc;
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wire puc;
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reg nmi;
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reg nmi;
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reg [13:0] irq;
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reg [13:0] irq;
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wire [13:0] irq_acc;
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wire [13:0] irq_acc;
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wire [13:0] irq_in;
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wire [13:0] irq_in;
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reg cpu_en;
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// Debug interface
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// Debug interface
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reg dbg_en;
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wire dbg_freeze;
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wire dbg_freeze;
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wire dbg_uart_txd;
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wire dbg_uart_txd;
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reg dbg_uart_rxd;
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reg dbg_uart_rxd;
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reg [15:0] dbg_uart_buf;
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reg [15:0] dbg_uart_buf;
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| Line 190... |
Line 192... |
end
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end
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initial
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initial
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begin
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begin
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reset_n = 1'b1;
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reset_n = 1'b1;
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#100;
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#93;
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reset_n = 1'b0;
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reset_n = 1'b0;
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#600;
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#593;
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reset_n = 1'b1;
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reset_n = 1'b1;
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end
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end
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initial
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initial
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begin
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begin
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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irq = 14'b0000;
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irq = 14'b0000;
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nmi = 1'b0;
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nmi = 1'b0;
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cpu_en = 1'b1;
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dbg_en = 1'b0;
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dbg_uart_rxd = 1'b1;
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dbg_uart_rxd = 1'b1;
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dbg_uart_buf = 16'h0000;
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dbg_uart_buf = 16'h0000;
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p1_din = 8'h00;
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p1_din = 8'h00;
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p2_din = 8'h00;
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p2_din = 8'h00;
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p3_din = 8'h00;
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p3_din = 8'h00;
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| Line 275... |
Line 279... |
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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// INPUTs
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// INPUTs
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.cpu_en (cpu_en), // Enable CPU code execution
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.dbg_en (dbg_en), // Debug interface enable
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_in), // Maskable interrupts
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.irq (irq_in), // Maskable interrupts
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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| Line 350... |
Line 356... |
.p5_din (p5_din), // Port 5 data input
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.p5_din (p5_din), // Port 5 data input
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.p6_din (p6_din), // Port 6 data input
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.p6_din (p6_din), // Port 6 data input
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
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);
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|
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//
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//
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// Timers
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// Timers
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| Line 380... |
Line 386... |
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.ta_cci0a (ta_cci0a), // Timer A compare 0 input A
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.ta_cci0a (ta_cci0a), // Timer A compare 0 input A
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.ta_cci0b (ta_cci0b), // Timer A compare 0 input B
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.ta_cci0b (ta_cci0b), // Timer A compare 0 input B
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.ta_cci1a (ta_cci1a), // Timer A compare 1 input A
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.ta_cci1a (ta_cci1a), // Timer A compare 1 input A
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| Line 406... |
Line 412... |
// INPUTs
|
// INPUTs
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
|
);
|
|
|
template_periph_16b template_periph_16b_0 (
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template_periph_16b template_periph_16b_0 (
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|
|
| Line 420... |
Line 426... |
// INPUTs
|
// INPUTs
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
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);
|
|
|
|
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//
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//
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