| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 151 $
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// $Rev: 154 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
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// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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| Line 153... |
Line 153... |
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// Scan (ASIC version only)
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// Scan (ASIC version only)
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reg scan_enable;
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reg scan_enable;
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reg scan_mode;
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reg scan_mode;
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// Debug interface
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// Debug interface: UART
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reg dbg_en;
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reg dbg_en;
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wire dbg_freeze;
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wire dbg_freeze;
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wire dbg_uart_txd;
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wire dbg_uart_txd;
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wire dbg_uart_rxd;
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wire dbg_uart_rxd;
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reg dbg_uart_rxd_sel;
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reg dbg_uart_rxd_sel;
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| Line 166... |
Line 166... |
reg dbg_uart_rxd_meta;
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reg dbg_uart_rxd_meta;
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reg [15:0] dbg_uart_buf;
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reg [15:0] dbg_uart_buf;
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reg dbg_uart_rx_busy;
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reg dbg_uart_rx_busy;
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reg dbg_uart_tx_busy;
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reg dbg_uart_tx_busy;
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// Debug interface: I2C
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wire dbg_scl;
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wire dbg_sda;
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wire dbg_scl_slave;
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wire dbg_scl_master;
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reg dbg_scl_master_sel;
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reg dbg_scl_master_dly;
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reg dbg_scl_master_pre;
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reg dbg_scl_master_meta;
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wire dbg_sda_slave_out;
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wire dbg_sda_slave_in;
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wire dbg_sda_master_out;
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reg dbg_sda_master_out_sel;
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reg dbg_sda_master_out_dly;
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reg dbg_sda_master_out_pre;
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reg dbg_sda_master_out_meta;
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wire dbg_sda_master_in;
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reg [15:0] dbg_i2c_buf;
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reg [8*32-1:0] dbg_i2c_string;
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// Core testbench debuging signals
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// Core testbench debuging signals
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] i_state;
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wire [8*32-1:0] e_state;
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wire [8*32-1:0] e_state;
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wire [31:0] inst_cycle;
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wire [31:0] inst_cycle;
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wire [8*32-1:0] inst_full;
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wire [8*32-1:0] inst_full;
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| Line 189... |
Line 209... |
// CPU & Memory registers
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// CPU & Memory registers
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`include "registers.v"
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`include "registers.v"
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// Debug interface tasks
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// Debug interface tasks
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`include "dbg_uart_tasks.v"
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`include "dbg_uart_tasks.v"
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`include "dbg_i2c_tasks.v"
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// Simple uart tasks
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// Simple uart tasks
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//`include "uart_tasks.v"
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//`include "uart_tasks.v"
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// Verilog stimulus
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// Verilog stimulus
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| Line 259... |
Line 280... |
dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_pre = 1'b1;
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dbg_uart_rxd_meta= 1'b0;
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dbg_uart_rxd_meta= 1'b0;
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dbg_uart_buf = 16'h0000;
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dbg_uart_buf = 16'h0000;
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dbg_uart_rx_busy = 1'b0;
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dbg_uart_rx_busy = 1'b0;
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dbg_uart_tx_busy = 1'b0;
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dbg_uart_tx_busy = 1'b0;
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dbg_scl_master_sel = 1'b0;
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dbg_scl_master_dly = 1'b1;
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dbg_scl_master_pre = 1'b1;
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dbg_scl_master_meta = 1'b0;
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dbg_sda_master_out_sel = 1'b0;
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dbg_sda_master_out_dly = 1'b1;
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dbg_sda_master_out_pre = 1'b1;
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dbg_sda_master_out_meta = 1'b0;
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dbg_i2c_string = "";
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p1_din = 8'h00;
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p1_din = 8'h00;
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p2_din = 8'h00;
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p2_din = 8'h00;
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p3_din = 8'h00;
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p3_din = 8'h00;
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p4_din = 8'h00;
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p4_din = 8'h00;
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p5_din = 8'h00;
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p5_din = 8'h00;
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| Line 325... |
Line 355... |
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// OUTPUTs
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// OUTPUTs
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.aclk (aclk), // ASIC ONLY: ACLK
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.aclk (aclk), // ASIC ONLY: ACLK
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.aclk_en (aclk_en), // FPGA ONLY: ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_i2c_sda_out (dbg_sda_slave_out), // Debug interface: I2C SDA OUT
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
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.dco_enable (dco_enable), // ASIC ONLY: Fast oscillator enable
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.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dco_wkup (dco_wkup), // ASIC ONLY: Fast oscillator wake-up (asynchronous)
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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| Line 351... |
Line 382... |
.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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.smclk_en (smclk_en), // FPGA ONLY: SMCLK enable
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// INPUTs
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// INPUTs
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.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
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.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
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.dbg_en (dbg_en), // Debug interface enable (asynchronous)
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.dbg_en (dbg_en), // Debug interface enable (asynchronous)
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.dbg_i2c_addr (I2C_ADDR), // Debug interface: I2C Address
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.dbg_i2c_broadcast (I2C_BROADCAST), // Debug interface: I2C Broadcast Address (for multicore systems)
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.dbg_i2c_scl (dbg_scl_slave), // Debug interface: I2C SCL
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.dbg_i2c_sda_in (dbg_sda_slave_in), // Debug interface: I2C SDA IN
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_in), // Maskable interrupts
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.irq (irq_in), // Maskable interrupts
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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| Line 573... |
Line 608... |
1'b0, // Vector 1 (0xFFE2)
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1'b0, // Vector 1 (0xFFE2)
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1'b0}; // Vector 0 (0xFFE0)
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1'b0}; // Vector 0 (0xFFE0)
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//
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//
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// I2C serial debug interface
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//----------------------------------
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// I2C Bus
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//.........................
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pullup dbg_scl_inst (dbg_scl);
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pullup dbg_sda_inst (dbg_sda);
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// I2C Slave (openMSP430)
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//.........................
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io_cell scl_slave_inst (
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.pad (dbg_scl), // I/O pad
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.data_in (dbg_scl_slave), // Input
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.data_out_en (1'b0), // Output enable
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.data_out (1'b0) // Output
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);
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io_cell sda_slave_inst (
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.pad (dbg_sda), // I/O pad
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.data_in (dbg_sda_slave_in), // Input
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.data_out_en (!dbg_sda_slave_out), // Output enable
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.data_out (1'b0) // Output
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);
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// I2C Master (Debugger)
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//.........................
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io_cell scl_master_inst (
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.pad (dbg_scl), // I/O pad
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.data_in (), // Input
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.data_out_en (!dbg_scl_master), // Output enable
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.data_out (1'b0) // Output
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);
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io_cell sda_master_inst (
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.pad (dbg_sda), // I/O pad
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.data_in (dbg_sda_master_in), // Input
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.data_out_en (!dbg_sda_master_out), // Output enable
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.data_out (1'b0) // Output
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);
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//
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// Debug utility signals
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// Debug utility signals
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//----------------------------------------
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//----------------------------------------
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msp_debug msp_debug_0 (
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msp_debug msp_debug_0 (
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|
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// OUTPUTs
|
// OUTPUTs
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