| Line 29... |
Line 29... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 154 $
|
// $Rev: 192 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
|
// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`include "timescale.v"
|
`include "timescale.v"
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
| Line 142... |
Line 142... |
wire smclk;
|
wire smclk;
|
wire smclk_en;
|
wire smclk_en;
|
reg reset_n;
|
reg reset_n;
|
wire puc_rst;
|
wire puc_rst;
|
reg nmi;
|
reg nmi;
|
reg [13:0] irq;
|
reg [`IRQ_NR-3:0] irq;
|
wire [13:0] irq_acc;
|
wire [`IRQ_NR-3:0] irq_acc;
|
wire [13:0] irq_in;
|
wire [`IRQ_NR-3:0] irq_in;
|
reg cpu_en;
|
reg cpu_en;
|
reg [13:0] wkup;
|
reg [13:0] wkup;
|
wire [13:0] wkup_in;
|
wire [13:0] wkup_in;
|
|
|
// Scan (ASIC version only)
|
// Scan (ASIC version only)
|
| Line 268... |
Line 268... |
|
|
initial
|
initial
|
begin
|
begin
|
error = 0;
|
error = 0;
|
stimulus_done = 1;
|
stimulus_done = 1;
|
irq = 14'h0000;
|
irq = {`IRQ_NR-2{1'b0}};
|
nmi = 1'b0;
|
nmi = 1'b0;
|
wkup = 14'h0000;
|
wkup = 14'h0000;
|
cpu_en = 1'b1;
|
cpu_en = 1'b1;
|
dbg_en = 1'b0;
|
dbg_en = 1'b0;
|
dbg_uart_rxd_sel = 1'b0;
|
dbg_uart_rxd_sel = 1'b0;
|
| Line 479... |
Line 479... |
|
|
// INPUTs
|
// INPUTs
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
.aclk_en (aclk_en), // ACLK enable (from CPU)
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
.dbg_freeze (dbg_freeze), // Freeze Timer A counter
|
.inclk (inclk), // INCLK external timer clock (SLOW)
|
.inclk (inclk), // INCLK external timer clock (SLOW)
|
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
|
.irq_ta0_acc (irq_acc[`IRQ_NR-7]),// Interrupt request TACCR0 accepted
|
.mclk (mclk), // Main system clock
|
.mclk (mclk), // Main system clock
|
.per_addr (per_addr), // Peripheral address
|
.per_addr (per_addr), // Peripheral address
|
.per_din (per_din), // Peripheral data input
|
.per_din (per_din), // Peripheral data input
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_en (per_en), // Peripheral enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
.per_we (per_we), // Peripheral write enable (high active)
|
| Line 589... |
Line 589... |
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 5 (0xFFEA)
|
1'b0, // Vector 4 (0xFFE8)
|
1'b0, // Vector 4 (0xFFE8)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port2, // Vector 3 (0xFFE6)
|
irq_port1, // Vector 2 (0xFFE4)
|
irq_port1, // Vector 2 (0xFFE4)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0, // Vector 1 (0xFFE2)
|
1'b0}; // Vector 0 (0xFFE0)
|
{`IRQ_NR-15{1'b0}}}; // Vector 0 (0xFFE0)
|
|
|
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
|
assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 12 (0xFFF8)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 11 (0xFFF6)
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
1'b0, // Vector 10 (0xFFF4) - Watchdog -
|
