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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 154 $
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// $Rev: 192 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
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// $LastChangedDate: 2013-12-17 21:15:28 +0100 (Tue, 17 Dec 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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Line 142... |
Line 142... |
wire smclk;
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wire smclk;
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wire smclk_en;
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wire smclk_en;
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reg reset_n;
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reg reset_n;
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wire puc_rst;
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wire puc_rst;
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reg nmi;
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reg nmi;
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reg [13:0] irq;
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reg [`IRQ_NR-3:0] irq;
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wire [13:0] irq_acc;
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wire [`IRQ_NR-3:0] irq_acc;
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wire [13:0] irq_in;
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wire [`IRQ_NR-3:0] irq_in;
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reg cpu_en;
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reg cpu_en;
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reg [13:0] wkup;
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reg [13:0] wkup;
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wire [13:0] wkup_in;
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wire [13:0] wkup_in;
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// Scan (ASIC version only)
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// Scan (ASIC version only)
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Line 268... |
Line 268... |
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initial
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initial
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begin
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begin
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error = 0;
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error = 0;
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stimulus_done = 1;
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stimulus_done = 1;
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irq = 14'h0000;
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irq = {`IRQ_NR-2{1'b0}};
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nmi = 1'b0;
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nmi = 1'b0;
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wkup = 14'h0000;
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wkup = 14'h0000;
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cpu_en = 1'b1;
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cpu_en = 1'b1;
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dbg_en = 1'b0;
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dbg_en = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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dbg_uart_rxd_sel = 1'b0;
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Line 479... |
Line 479... |
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// INPUTs
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// INPUTs
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.aclk_en (aclk_en), // ACLK enable (from CPU)
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.aclk_en (aclk_en), // ACLK enable (from CPU)
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.dbg_freeze (dbg_freeze), // Freeze Timer A counter
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.dbg_freeze (dbg_freeze), // Freeze Timer A counter
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.inclk (inclk), // INCLK external timer clock (SLOW)
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.inclk (inclk), // INCLK external timer clock (SLOW)
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.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.irq_ta0_acc (irq_acc[`IRQ_NR-7]),// Interrupt request TACCR0 accepted
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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Line 589... |
Line 589... |
1'b0, // Vector 5 (0xFFEA)
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1'b0, // Vector 5 (0xFFEA)
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1'b0, // Vector 4 (0xFFE8)
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1'b0, // Vector 4 (0xFFE8)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port2, // Vector 3 (0xFFE6)
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irq_port1, // Vector 2 (0xFFE4)
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irq_port1, // Vector 2 (0xFFE4)
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1'b0, // Vector 1 (0xFFE2)
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1'b0, // Vector 1 (0xFFE2)
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1'b0}; // Vector 0 (0xFFE0)
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{`IRQ_NR-15{1'b0}}}; // Vector 0 (0xFFE0)
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assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
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assign wkup_in = wkup | {1'b0, // Vector 13 (0xFFFA)
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1'b0, // Vector 12 (0xFFF8)
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1'b0, // Vector 12 (0xFFF8)
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1'b0, // Vector 11 (0xFFF6)
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1'b0, // Vector 11 (0xFFF6)
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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1'b0, // Vector 10 (0xFFF4) - Watchdog -
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