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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 23 $
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// $Rev: 33 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
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// $LastChangedDate: 2009-12-29 19:18:00 +0100 (Tue, 29 Dec 2009) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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Line 43... |
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//
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//
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// Wire & Register definition
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// Wire & Register definition
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//------------------------------
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//------------------------------
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// RAM interface
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// Data Memory interface
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wire [`RAM_MSB:0] ram_addr;
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wire [`DMEM_MSB:0] dmem_addr;
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wire ram_cen;
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wire dmem_cen;
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wire [15:0] ram_din;
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wire [15:0] dmem_din;
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wire [1:0] ram_wen;
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wire [1:0] dmem_wen;
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wire [15:0] ram_dout;
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wire [15:0] dmem_dout;
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// ROM interface
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// Program Memory interface
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wire [`ROM_MSB:0] rom_addr;
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wire [`PMEM_MSB:0] pmem_addr;
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wire rom_cen;
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wire pmem_cen;
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wire [15:0] rom_din_dbg;
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wire [15:0] pmem_din;
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wire [1:0] rom_wen_dbg;
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wire [1:0] pmem_wen;
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wire [15:0] rom_dout;
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wire [15:0] pmem_dout;
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// Peripherals interface
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// Peripherals interface
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wire [7:0] per_addr;
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wire [7:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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| Line 168... |
Line 168... |
//
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//
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// Initialize ROM
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// Initialize ROM
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//------------------------------
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//------------------------------
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initial
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initial
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begin
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begin
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$readmemh("./rom.mem", rom_0.mem);
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$readmemh("./pmem.mem", pmem_0.mem);
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end
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end
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//
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//
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// Generate Clock & Reset
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// Generate Clock & Reset
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//------------------------------
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//------------------------------
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| Line 220... |
Line 220... |
ta_cci2b = 1'b0;
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ta_cci2b = 1'b0;
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end
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end
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//
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//
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// ROM
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// Program Memory
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//----------------------------------
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//----------------------------------
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ram #(`ROM_MSB) rom_0 (
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ram #(`PMEM_MSB) pmem_0 (
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// OUTPUTs
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// OUTPUTs
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.ram_dout (rom_dout), // ROM data output
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.ram_dout (pmem_dout), // Program Memory data output
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// INPUTs
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// INPUTs
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.ram_addr (rom_addr), // ROM address
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.ram_addr (pmem_addr), // Program Memory address
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.ram_cen (rom_cen), // ROM chip enable (low active)
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.ram_cen (pmem_cen), // Program Memory chip enable (low active)
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.ram_clk (mclk), // ROM clock
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.ram_clk (mclk), // Program Memory clock
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.ram_din (rom_din_dbg), // ROM data input
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.ram_din (pmem_din), // Program Memory data input
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.ram_wen (rom_wen_dbg) // ROM write enable (low active)
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.ram_wen (pmem_wen) // Program Memory write enable (low active)
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);
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);
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//
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//
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// RAM
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// Data Memory
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//----------------------------------
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//----------------------------------
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ram #(`RAM_MSB) ram_0 (
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ram #(`DMEM_MSB) dmem_0 (
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// OUTPUTs
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// OUTPUTs
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.ram_dout (ram_dout), // RAM data output
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.ram_dout (dmem_dout), // Data Memory data output
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// INPUTs
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// INPUTs
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.ram_addr (ram_addr), // RAM address
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.ram_addr (dmem_addr), // Data Memory address
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.ram_cen (ram_cen), // RAM chip enable (low active)
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.ram_cen (dmem_cen), // Data Memory chip enable (low active)
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.ram_clk (mclk), // RAM clock
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.ram_clk (mclk), // Data Memory clock
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.ram_din (ram_din), // RAM data input
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.ram_din (dmem_din), // Data Memory data input
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.ram_wen (ram_wen) // RAM write enable (low active)
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.ram_wen (dmem_wen) // Data Memory write enable (low active)
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);
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);
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//
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//
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// openMSP430 Instance
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// openMSP430 Instance
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| Line 265... |
Line 265... |
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// OUTPUTs
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// OUTPUTs
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.aclk_en (aclk_en), // ACLK enable
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.aclk_en (aclk_en), // ACLK enable
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_freeze (dbg_freeze), // Freeze peripherals
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
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.dmem_addr (dmem_addr), // Data Memory address
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.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
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.dmem_din (dmem_din), // Data Memory data input
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.ram_addr (ram_addr), // RAM address
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.ram_cen (ram_cen), // RAM chip enable (low active)
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.ram_din (ram_din), // RAM data input
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.ram_wen (ram_wen), // RAM write enable (low active)
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.rom_addr (rom_addr), // ROM address
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.rom_cen (rom_cen), // ROM chip enable (low active)
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.rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE--
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.rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF--
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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// INPUTs
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// INPUTs
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_in), // Maskable interrupts
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.irq (irq_in), // Maskable interrupts
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.nmi (nmi), // Non-maskable interrupt (asynchronous)
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.per_dout (per_dout), // Peripheral data output
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.per_dout (per_dout), // Peripheral data output
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.ram_dout (ram_dout), // RAM data output
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.pmem_dout (pmem_dout), // Program Memory data output
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.reset_n (reset_n), // Reset Pin (low active)
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.reset_n (reset_n) // Reset Pin (low active)
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.rom_dout (rom_dout) // ROM data output
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);
|
);
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//
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//
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// Digital I/O
|
// Digital I/O
|
//----------------------------------
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//----------------------------------
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