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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [tb_openMSP430.v] - Diff between revs 65 and 67

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Rev 65 Rev 67
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 65 $
// $Rev: 67 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-24 22:48:34 +0100 (Wed, 24 Feb 2010) $
// $LastChangedDate: 2010-03-07 12:59:38 +0100 (Sun, 07 Mar 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
 
 
Line 487... Line 487...
// End of simulation
// End of simulation
//----------------------------------------
//----------------------------------------
 
 
initial // Timeout
initial // Timeout
  begin
  begin
 
   `ifdef NO_TIMEOUT
 
   `else
    `ifdef LONG_TIMEOUT
    `ifdef LONG_TIMEOUT
     #5000000;
     #5000000;
   `else
   `else
     #500000;
     #500000;
   `endif
   `endif
     $display(" ===============================================");
     $display(" ===============================================");
     $display("|               SIMULATION FAILED               |");
     $display("|               SIMULATION FAILED               |");
     $display("|              (simulation Timeout)             |");
     $display("|              (simulation Timeout)             |");
     $display(" ===============================================");
     $display(" ===============================================");
     $finish;
     $finish;
 
   `endif
  end
  end
 
 
initial // Normal end of test
initial // Normal end of test
  begin
  begin
     @(inst_pc===16'hffff)
     @(inst_pc===16'hffff)

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