| Line 33... |
Line 33... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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module omsp_clock_module (
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module omsp_clock_module (
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// OUTPUTs
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// OUTPUTs
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aclk_en, // ACLK enable
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aclk_en, // ACLK enable
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cpu_en_s, // Enable CPU code execution (synchronous)
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dbg_clk, // Debug unit clock
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dbg_en_s, // Debug interface enable (synchronous)
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dbg_rst, // Debug unit reset
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mclk, // Main system clock
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mclk, // Main system clock
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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por, // Power-on reset
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por, // Power-on reset
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puc, // Main system reset
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puc, // Main system reset
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smclk_en, // SMCLK enable
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smclk_en, // SMCLK enable
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// INPUTs
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// INPUTs
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dbg_reset, // Reset CPU from debug interface
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cpu_en, // Enable CPU code execution (asynchronous)
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dbg_cpu_reset, // Reset CPU from debug interface
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dbg_en, // Debug interface enable (asynchronous)
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dco_clk, // Fast oscillator (fast clock)
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dco_clk, // Fast oscillator (fast clock)
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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lfxt_clk, // Low frequency oscillator (typ 32kHz)
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oscoff, // Turns off LFXT1 clock input
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oscoff, // Turns off LFXT1 clock input
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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reset_n, // Reset Pin (low active)
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reset_n, // Reset Pin (low active, asynchronous)
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scg1, // System clock generator 1. Turns off the SMCLK
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scg1, // System clock generator 1. Turns off the SMCLK
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wdt_reset // Watchdog-timer reset
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wdt_reset // Watchdog-timer reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output aclk_en; // ACLK enable
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output aclk_en; // ACLK enable
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output cpu_en_s; // Enable CPU code execution (synchronous)
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output dbg_clk; // Debug unit clock
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output dbg_en_s; // Debug unit enable (synchronous)
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output dbg_rst; // Debug unit reset
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output mclk; // Main system clock
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output mclk; // Main system clock
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output [15:0] per_dout; // Peripheral data output
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output [15:0] per_dout; // Peripheral data output
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output por; // Power-on reset
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output por; // Power-on reset
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output puc; // Main system reset
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output puc; // Main system reset
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output smclk_en; // SMCLK enable
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output smclk_en; // SMCLK enable
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_reset; // Reset CPU from debug interface
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input cpu_en; // Enable CPU code execution (asynchronous)
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input dbg_cpu_reset;// Reset CPU from debug interface
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input dbg_en; // Debug interface enable (asynchronous)
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input dco_clk; // Fast oscillator (fast clock)
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input dco_clk; // Fast oscillator (fast clock)
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input lfxt_clk; // Low frequency oscillator (typ 32kHz)
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input oscoff; // Turns off LFXT1 clock input
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input oscoff; // Turns off LFXT1 clock input
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input reset_n; // Reset Pin (low active)
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input reset_n; // Reset Pin (low active, asynchronous)
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input scg1; // System clock generator 1. Turns off the SMCLK
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input scg1; // System clock generator 1. Turns off the SMCLK
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input wdt_reset; // Watchdog-timer reset
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input wdt_reset; // Watchdog-timer reset
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//=============================================================================
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//=============================================================================
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Line 129... |
(BCSCTL2 /2): reg_dec = BCSCTL2_D;
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(BCSCTL2 /2): reg_dec = BCSCTL2_D;
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default : reg_dec = {256{1'b0}};
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default : reg_dec = {256{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_lo_write = per_wen[0] & per_en;
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wire reg_lo_write = per_we[0] & per_en;
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wire reg_hi_write = per_wen[1] & per_en;
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wire reg_hi_write = per_we[1] & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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Line 181... |
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//=============================================================================
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//=============================================================================
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// 5) CLOCK GENERATION
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// 5) CLOCK GENERATION
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//=============================================================================
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//=============================================================================
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// Synchronize CPU_EN signal
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//---------------------------------------
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reg [1:0] cpu_en_sync;
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always @ (posedge mclk or posedge por)
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if (por) cpu_en_sync <= 2'b00;
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else cpu_en_sync <= {cpu_en_sync[0], cpu_en};
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assign cpu_en_s = cpu_en_sync[1];
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// Synchronize LFXT_CLK & edge detection
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// Synchronize LFXT_CLK & edge detection
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//---------------------------------------
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//---------------------------------------
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reg [2:0] lfxt_clk_s;
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reg [2:0] lfxt_clk_s;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge por)
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if (puc) lfxt_clk_s <= 3'b000;
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if (por) lfxt_clk_s <= 3'b000;
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else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
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else lfxt_clk_s <= {lfxt_clk_s[1:0], lfxt_clk};
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wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
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wire lfxt_clk_en = (lfxt_clk_s[1] & ~lfxt_clk_s[2]) & ~(oscoff & ~bcsctl2[`SELS]);
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Line 222... |
(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
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(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
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&aclk_div[2:0]);
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&aclk_div[2:0]);
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) aclk_en <= 1'b0;
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if (puc) aclk_en <= 1'b0;
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else aclk_en <= aclk_en_nxt;
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else aclk_en <= aclk_en_nxt & cpu_en_s;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) aclk_div <= 3'h0;
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if (puc) aclk_div <= 3'h0;
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else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
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else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
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Line 244... |
(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
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(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
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&smclk_div[2:0]);
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&smclk_div[2:0]);
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) smclk_en <= 1'b0;
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if (puc) smclk_en <= 1'b0;
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else smclk_en <= smclk_en_nxt;
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else smclk_en <= smclk_en_nxt & cpu_en_s;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) smclk_div <= 3'h0;
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if (puc) smclk_div <= 3'h0;
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else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
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else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
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// Generate DBG_CLK
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//----------------------------
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assign dbg_clk = mclk;
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//=============================================================================
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//=============================================================================
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// 6) RESET GENERATION
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// 6) RESET GENERATION
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//=============================================================================
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//=============================================================================
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// Generate synchronized POR
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// Generate synchronized POR
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wire por_reset = !reset_n;
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wire por_reset_a = !reset_n;
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reg [1:0] por_s;
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reg [1:0] por_s;
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always @(posedge mclk_n or posedge por_reset)
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always @(posedge mclk or posedge por_reset_a)
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if (por_reset) por_s <= 2'b11;
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if (por_reset_a) por_s <= 2'b11;
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else por_s <= {por_s[0], 1'b0};
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else por_s <= {por_s[0], 1'b0};
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wire por = por_s[1];
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wire por = por_s[1];
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// Generate main system reset
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// Generate main system reset
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wire puc_reset = por_reset | wdt_reset | dbg_reset;
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wire puc_reset = por | wdt_reset | dbg_cpu_reset;
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reg [1:0] puc_s;
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reg [1:0] puc_s;
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always @(posedge mclk_n or posedge puc_reset)
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always @(posedge mclk or posedge puc_reset)
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if (puc_reset) puc_s <= 2'b11;
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if (puc_reset) puc_s <= 2'b11;
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else puc_s <= {puc_s[0], 1'b0};
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else puc_s <= {puc_s[0], 1'b0};
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wire puc = puc_s[1];
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wire puc = puc_s[1];
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// Generate debug unit reset
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`ifdef DBG_EN
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reg [1:0] dbg_rst_s;
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always @(posedge mclk or posedge por)
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if (por) dbg_rst_s <= 2'b11;
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else dbg_rst_s <= {dbg_rst_s[0], ~dbg_en};
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`else
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wire [1:0] dbg_rst_s = 2'b11;
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`endif
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wire dbg_en_s = ~dbg_rst_s[1];
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wire dbg_rst = dbg_rst_s[1];
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endmodule // omsp_clock_module
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endmodule // omsp_clock_module
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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