| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 134 $
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// $Rev: 180 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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// $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 192... |
Line 192... |
//--------------
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//--------------
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reg [7:0] bcsctl1;
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reg [7:0] bcsctl1;
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wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
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wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1];
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wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
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wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0];
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|
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`ifdef ASIC
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`ifdef ASIC_CLOCKING
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`ifdef ACLK_DIVIDER
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`ifdef ACLK_DIVIDER
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wire [7:0] divax_mask = 8'h30;
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wire [7:0] divax_mask = 8'h30;
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`else
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`else
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wire [7:0] divax_mask = 8'h00;
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wire [7:0] divax_mask = 8'h00;
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`endif
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`endif
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| Line 223... |
Line 223... |
`ifdef MCLK_DIVIDER
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`ifdef MCLK_DIVIDER
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wire [7:0] divmx_mask = 8'h30;
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wire [7:0] divmx_mask = 8'h30;
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`else
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`else
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wire [7:0] divmx_mask = 8'h00;
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wire [7:0] divmx_mask = 8'h00;
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`endif
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`endif
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`ifdef ASIC
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`ifdef ASIC_CLOCKING
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`ifdef SMCLK_MUX
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`ifdef SMCLK_MUX
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wire [7:0] sels_mask = 8'h08;
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wire [7:0] sels_mask = 8'h08;
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`else
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`else
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wire [7:0] sels_mask = 8'h00;
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wire [7:0] sels_mask = 8'h00;
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`endif
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`endif
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| Line 261... |
Line 261... |
|
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//=============================================================================
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//=============================================================================
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// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
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// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...)
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//=============================================================================
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//=============================================================================
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|
|
`ifdef ASIC
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`ifdef ASIC_CLOCKING
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wire cpuoff_and_mclk_enable;
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wire cpuoff_and_mclk_enable;
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omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
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omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable));
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`endif
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`endif
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|
|
//-----------------------------------------------------------
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//-----------------------------------------------------------
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| Line 374... |
Line 374... |
// ASIC MODE
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// ASIC MODE
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//------------------------------------------------
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//------------------------------------------------
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// Note: unlike the original MSP430 specification,
|
// Note: unlike the original MSP430 specification,
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// we allow to switch off the LFXT even
|
// we allow to switch off the LFXT even
|
// if it is selected by MCLK or SMCLK.
|
// if it is selected by MCLK or SMCLK.
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
|
|
`ifdef OSCOFF_EN
|
`ifdef OSCOFF_EN
|
|
|
// The LFXT is synchronously disabled if:
|
// The LFXT is synchronously disabled if:
|
// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
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// - the cpu pin is disabled (in that case, wait for mclk_enable==0)
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| Line 524... |
Line 524... |
`endif
|
`endif
|
|
|
// Synchronize CPU_EN signal to the SMCLK domain
|
// Synchronize CPU_EN signal to the SMCLK domain
|
//----------------------------------------------
|
//----------------------------------------------
|
// Note: the synchronizer is only required if there is a SMCLK_MUX
|
// Note: the synchronizer is only required if there is a SMCLK_MUX
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
`ifdef SMCLK_MUX
|
`ifdef SMCLK_MUX
|
wire cpu_en_sm_s;
|
wire cpu_en_sm_s;
|
omsp_sync_cell sync_cell_cpu_sm_en (
|
omsp_sync_cell sync_cell_cpu_sm_en (
|
.data_out (cpu_en_sm_s),
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.data_out (cpu_en_sm_s),
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.data_in (cpu_en),
|
.data_in (cpu_en),
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| Line 623... |
Line 623... |
// 6.3) ACLK GENERATION
|
// 6.3) ACLK GENERATION
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
// ASIC MODE
|
// ASIC MODE
|
//----------------------------
|
//----------------------------
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
|
|
`ifdef ACLK_DIVIDER
|
`ifdef ACLK_DIVIDER
|
`ifdef LFXT_DOMAIN
|
`ifdef LFXT_DOMAIN
|
|
|
wire nodiv_aclk = lfxt_clk;
|
wire nodiv_aclk = lfxt_clk;
|
| Line 756... |
Line 756... |
`endif
|
`endif
|
|
|
|
|
// ASIC MODE
|
// ASIC MODE
|
//----------------------------
|
//----------------------------
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
`ifdef SMCLK_MUX
|
`ifdef SMCLK_MUX
|
|
|
// Synchronizers
|
// Synchronizers
|
//------------------------------------------------------
|
//------------------------------------------------------
|
// When the SMCLK MUX is enabled, the reset and DIVSx
|
// When the SMCLK MUX is enabled, the reset and DIVSx
|
| Line 914... |
Line 914... |
|
|
|
|
// Serial Debug Interface Clock gate
|
// Serial Debug Interface Clock gate
|
//------------------------------------------------
|
//------------------------------------------------
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
`ifdef ASIC
|
`ifdef ASIC_CLOCKING
|
omsp_clock_gate clock_gate_dbg_clk (
|
omsp_clock_gate clock_gate_dbg_clk (
|
.gclk (dbg_clk),
|
.gclk (dbg_clk),
|
.clk (mclk),
|
.clk (mclk),
|
.enable (dbg_en_s),
|
.enable (dbg_en_s),
|
.scan_enable (scan_enable)
|
.scan_enable (scan_enable)
|
