| Line 49... |
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// INPUTs
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// INPUTs
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clk_in0, // Clock input 0
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clk_in0, // Clock input 0
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clk_in1, // Clock input 1
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clk_in1, // Clock input 1
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reset, // Reset
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reset, // Reset
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scan_mode, // Scan mode (clk_in0 is selected in scan mode)
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scan_mode, // Scan mode (clk_in0 is selected in scan mode)
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select // Clock selection
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select_in // Clock selection
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output clk_out; // Clock output
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output clk_out; // Clock output
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| Line 62... |
Line 62... |
//=========
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//=========
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input clk_in0; // Clock input 0
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input clk_in0; // Clock input 0
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input clk_in1; // Clock input 1
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input clk_in1; // Clock input 1
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input reset; // Reset
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input reset; // Reset
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input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
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input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
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input select; // Clock selection
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input select_in; // Clock selection
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//===========================================================================================================================//
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//===========================================================================================================================//
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// 1) CLOCK MUX //
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// 1) CLOCK MUX //
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//===========================================================================================================================//
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//===========================================================================================================================//
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| Line 75... |
Line 75... |
// //
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// //
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// //
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// //
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// //
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// //
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// //
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// //
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// +-----. +--------+ +--------+ //
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// +-----. +--------+ +--------+ //
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// select >>----+-------------O| \ | | | | +-----. //
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// select_in >>----+-------------O| \ | | | | +-----. //
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// | | |---| D Q |---| D Q |--+-------| \ //
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// | | |---| D Q |---| D Q |--+-------| \ //
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// | +-------O| / | | | | | | |O-+ //
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// | +-------O| / | | | | | | |O-+ //
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// | | +-----' | | | | | +--O| / | //
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// | | +-----' | | | | | +--O| / | //
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// | | | /\ | | /\ | | | +-----' | //
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// | | | /\ | | /\ | | | +-----' | //
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// | | +--+--+--+ +--+--+--+ | | | //
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// | | +--+--+--+ +--+--+--+ | | | //
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|
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// CLK_IN0 Selection
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// CLK_IN0 Selection
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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|
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assign in0_select = ~select & ~in1_select_ss;
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assign in0_select = ~select_in & ~in1_select_ss;
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always @ (posedge clk_in0_inv or posedge reset)
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always @ (posedge clk_in0_inv or posedge reset)
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if (reset) in0_select_s <= 1'b1;
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if (reset) in0_select_s <= 1'b1;
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else in0_select_s <= in0_select;
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else in0_select_s <= in0_select;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// CLK_IN1 Selection
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// CLK_IN1 Selection
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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|
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assign in1_select = select & ~in0_select_ss;
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assign in1_select = select_in & ~in0_select_ss;
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always @ (posedge clk_in1_inv or posedge reset)
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always @ (posedge clk_in1_inv or posedge reset)
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if (reset) in1_select_s <= 1'b0;
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if (reset) in1_select_s <= 1'b0;
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else in1_select_s <= in1_select;
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else in1_select_s <= in1_select;
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endmodule // omsp_clock_gate
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endmodule // omsp_clock_gate
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No newline at end of file
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No newline at end of file
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