| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 70... |
Line 70... |
eu_mdb_out, // Memory data bus output
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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fe_mb_en, // Frontend Memory bus enable
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fe_mdb_in, // Frontend Memory data bus input
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fe_mdb_in, // Frontend Memory data bus input
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pc, // Program counter
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pc, // Program counter
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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|
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output dbg_freeze; // Freeze peripherals
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output dbg_freeze; // Freeze peripherals
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| Line 105... |
Line 105... |
input [15:0] eu_mdb_out; // Memory data bus output
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input fe_mb_en; // Frontend Memory bus enable
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input puc; // Main system reset
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input puc_rst; // Main system reset
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|
|
|
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//=============================================================================
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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// 1) WIRE & PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 210... |
Line 210... |
|
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// PUC is localy used as a data.
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// PUC is localy used as a data.
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reg [1:0] puc_sync;
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reg [1:0] puc_sync;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) puc_sync <= 2'b11;
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if (dbg_rst) puc_sync <= 2'b11;
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else puc_sync <= {puc_sync[0] , puc};
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else puc_sync <= {puc_sync[0] , puc_rst};
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wire puc_s = puc_sync[1];
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wire puc_s = puc_sync[1];
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|
|
|
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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| Line 275... |
Line 275... |
// 3) REGISTER: CORE INTERFACE
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// 3) REGISTER: CORE INTERFACE
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//=============================================================================
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//=============================================================================
|
|
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// CPU_ID Register
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// CPU_ID Register
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//-----------------
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//-----------------
|
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// -------------------------------------------------------------------
|
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// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
|
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// |----------------------------+-----------------+------+-------------|
|
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// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
|
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// --------------------------------------------------------------------
|
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// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
|
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// |----------------------------+-------------------------------+------|
|
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// | PMEM_SIZE | DMEM_SIZE | MPY |
|
|
// -------------------------------------------------------------------
|
|
|
|
wire [2:0] cpu_version = `CPU_VERSION;
|
|
`ifdef ASIC
|
|
wire cpu_asic = 1'b1;
|
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`else
|
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wire cpu_asic = 1'b0;
|
|
`endif
|
|
wire [4:0] user_version = `USER_VERSION;
|
|
wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size
|
|
`ifdef MULTIPLIER
|
|
wire mpy_info = 1'b1;
|
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`else
|
|
wire mpy_info = 1'b0;
|
|
`endif
|
|
wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size
|
|
wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
|
|
|
wire [15:0] cpu_id_pmem = `PMEM_SIZE;
|
wire [31:0] cpu_id = {pmem_size,
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wire [15:0] cpu_id_dmem = `DMEM_SIZE;
|
dmem_size,
|
wire [31:0] cpu_id = {cpu_id_pmem, cpu_id_dmem};
|
mpy_info,
|
|
per_space,
|
|
user_version,
|
|
cpu_asic,
|
|
cpu_version};
|
|
|
|
|
// CPU_CTL Register
|
// CPU_CTL Register
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// 7 6 5 4 3 2 1 0
|
// 7 6 5 4 3 2 1 0
|
