| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 149 $
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// $Rev: 154 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-07-19 22:21:12 +0200 (Thu, 19 Jul 2012) $
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// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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|
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module omsp_dbg (
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module omsp_dbg (
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// OUTPUTs
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// OUTPUTs
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dbg_cpu_reset, // Reset CPU from debug interface
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dbg_freeze, // Freeze peripherals
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dbg_freeze, // Freeze peripherals
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dbg_halt_cmd, // Halt CPU command
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dbg_halt_cmd, // Halt CPU command
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dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
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dbg_mem_addr, // Debug address for rd/wr access
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dbg_mem_addr, // Debug address for rd/wr access
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dbg_mem_dout, // Debug unit data output
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dbg_mem_dout, // Debug unit data output
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dbg_mem_en, // Debug unit memory enable
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dbg_mem_en, // Debug unit memory enable
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dbg_mem_wr, // Debug unit memory write
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dbg_mem_wr, // Debug unit memory write
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dbg_reg_wr, // Debug unit CPU register write
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dbg_reg_wr, // Debug unit CPU register write
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dbg_cpu_reset, // Reset CPU from debug interface
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_uart_txd, // Debug interface: UART TXD
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// INPUTs
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// INPUTs
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cpu_en_s, // Enable CPU code execution (synchronous)
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cpu_en_s, // Enable CPU code execution (synchronous)
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cpu_id, // CPU ID
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cpu_id, // CPU ID
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cpu_nr_inst, // Current oMSP instance number
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cpu_nr_total, // Total number of oMSP instances-1
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dbg_clk, // Debug unit clock
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dbg_clk, // Debug unit clock
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dbg_en_s, // Debug interface enable (synchronous)
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dbg_en_s, // Debug interface enable (synchronous)
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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dbg_i2c_addr, // Debug interface: I2C Address
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dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
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dbg_i2c_scl, // Debug interface: I2C SCL
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dbg_i2c_sda_in, // Debug interface: I2C SDA IN
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dbg_mem_din, // Debug unit Memory data input
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dbg_mem_din, // Debug unit Memory data input
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dbg_reg_din, // Debug unit CPU register data input
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dbg_reg_din, // Debug unit CPU register data input
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dbg_rst, // Debug unit reset
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dbg_rst, // Debug unit reset
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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decode_noirq, // Frontend decode instruction
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decode_noirq, // Frontend decode instruction
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| Line 81... |
Line 88... |
puc_pnd_set // PUC pending set for the serial debug interface
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puc_pnd_set // PUC pending set for the serial debug interface
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output dbg_cpu_reset; // Reset CPU from debug interface
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output dbg_freeze; // Freeze peripherals
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output dbg_freeze; // Freeze peripherals
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output dbg_halt_cmd; // Halt CPU command
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output dbg_halt_cmd; // Halt CPU command
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output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
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output [15:0] dbg_mem_addr; // Debug address for rd/wr access
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output [15:0] dbg_mem_addr; // Debug address for rd/wr access
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output [15:0] dbg_mem_dout; // Debug unit data output
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output [15:0] dbg_mem_dout; // Debug unit data output
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output dbg_mem_en; // Debug unit memory enable
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output dbg_mem_en; // Debug unit memory enable
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output [1:0] dbg_mem_wr; // Debug unit memory write
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output [1:0] dbg_mem_wr; // Debug unit memory write
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output dbg_reg_wr; // Debug unit CPU register write
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output dbg_reg_wr; // Debug unit CPU register write
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output dbg_cpu_reset; // Reset CPU from debug interface
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output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_uart_txd; // Debug interface: UART TXD
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// INPUTs
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// INPUTs
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//=========
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//=========
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input cpu_en_s; // Enable CPU code execution (synchronous)
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input cpu_en_s; // Enable CPU code execution (synchronous)
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input [31:0] cpu_id; // CPU ID
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input [31:0] cpu_id; // CPU ID
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input [7:0] cpu_nr_inst; // Current oMSP instance number
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input [7:0] cpu_nr_total; // Total number of oMSP instances-1
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input dbg_clk; // Debug unit clock
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input dbg_clk; // Debug unit clock
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input dbg_en_s; // Debug interface enable (synchronous)
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input dbg_en_s; // Debug interface enable (synchronous)
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input dbg_halt_st; // Halt/Run status from CPU
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input dbg_halt_st; // Halt/Run status from CPU
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input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
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input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
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input dbg_i2c_scl; // Debug interface: I2C SCL
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input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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input dbg_rst; // Debug unit reset
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input dbg_rst; // Debug unit reset
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input decode_noirq; // Frontend decode instruction
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input decode_noirq; // Frontend decode instruction
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| Line 146... |
Line 160... |
wire brk3_halt;
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wire brk3_halt;
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wire brk3_pnd;
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wire brk3_pnd;
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wire [15:0] brk3_dout;
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wire [15:0] brk3_dout;
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// Number of registers
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// Number of registers
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parameter NR_REG = 24;
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parameter NR_REG = 25;
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// Register addresses
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// Register addresses
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parameter CPU_ID_LO = 6'h00;
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parameter CPU_ID_LO = 6'h00;
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parameter CPU_ID_HI = 6'h01;
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parameter CPU_ID_HI = 6'h01;
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parameter CPU_CTL = 6'h02;
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parameter CPU_CTL = 6'h02;
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| Line 181... |
Line 195... |
parameter BRK3_CTL = 6'h14;
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parameter BRK3_CTL = 6'h14;
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parameter BRK3_STAT = 6'h15;
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parameter BRK3_STAT = 6'h15;
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parameter BRK3_ADDR0 = 6'h16;
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parameter BRK3_ADDR0 = 6'h16;
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parameter BRK3_ADDR1 = 6'h17;
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parameter BRK3_ADDR1 = 6'h17;
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`endif
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`endif
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parameter CPU_NR = 6'h18;
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// Register one-hot decoder
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// Register one-hot decoder
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parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
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parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
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parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
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parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
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parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
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parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
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| Line 216... |
Line 231... |
parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
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parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
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parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
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parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
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parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
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parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
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parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
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parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
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`endif
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`endif
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parameter CPU_NR_D = (BASE_D << CPU_NR);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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| Line 261... |
Line 277... |
BRK3_CTL : reg_dec = BRK3_CTL_D;
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BRK3_CTL : reg_dec = BRK3_CTL_D;
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BRK3_STAT : reg_dec = BRK3_STAT_D;
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BRK3_STAT : reg_dec = BRK3_STAT_D;
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BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
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BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
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BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
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BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
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`endif
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`endif
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CPU_NR : reg_dec = CPU_NR_D;
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// pragma coverage off
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// pragma coverage off
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default: reg_dec = {NR_REG{1'b0}};
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default: reg_dec = {NR_REG{1'b0}};
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// pragma coverage on
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// pragma coverage on
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endcase
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endcase
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| Line 294... |
Line 311... |
// -------------------------------------------------------------------
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// -------------------------------------------------------------------
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// This register is assigned in the SFR module
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// This register is assigned in the SFR module
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// CPU_NR Register
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//-----------------
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// -------------------------------------------------------------------
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// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
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// |---------------------------------+---------------------------------|
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// | CPU_TOTAL_NR | CPU_INST_NR |
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// -------------------------------------------------------------------
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wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
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// CPU_CTL Register
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// CPU_CTL Register
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// 7 6 5 4 3 2 1 0
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// 7 6 5 4 3 2 1 0
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// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
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// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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| Line 612... |
Line 640... |
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
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wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
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wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
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wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
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wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
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wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
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wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
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wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
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wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
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wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
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wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
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wire [15:0] dbg_dout = cpu_id_lo_rd |
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wire [15:0] dbg_dout = cpu_id_lo_rd |
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cpu_id_hi_rd |
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cpu_id_hi_rd |
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cpu_ctl_rd |
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cpu_ctl_rd |
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cpu_stat_rd |
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cpu_stat_rd |
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| Line 624... |
Line 653... |
mem_addr_rd |
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mem_addr_rd |
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mem_cnt_rd |
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mem_cnt_rd |
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brk0_dout |
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brk0_dout |
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brk1_dout |
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brk1_dout |
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brk2_dout |
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brk2_dout |
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brk3_dout;
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brk3_dout |
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cpu_nr_rd;
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// Tell UART/JTAG interface that the data is ready to be read
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// Tell UART/I2C interface that the data is ready to be read
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) dbg_rd_rdy <= 1'b0;
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if (dbg_rst) dbg_rd_rdy <= 1'b0;
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else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
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else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
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else dbg_rd_rdy <= dbg_rd;
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else dbg_rd_rdy <= dbg_rd;
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|
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| Line 701... |
Line 731... |
always @(posedge dbg_clk or posedge dbg_rst)
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always @(posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) mem_burst <= 1'b0;
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if (dbg_rst) mem_burst <= 1'b0;
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else if (mem_burst_start) mem_burst <= 1'b1;
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else if (mem_burst_start) mem_burst <= 1'b1;
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else if (mem_burst_end) mem_burst <= 1'b0;
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else if (mem_burst_end) mem_burst <= 1'b0;
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|
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// Control signals for UART/JTAG interface
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// Control signals for UART/I2C interface
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assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
|
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
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assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
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assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
|
|
|
// Trigger CPU Register or memory access during a burst
|
// Trigger CPU Register or memory access during a burst
|
reg mem_startb;
|
reg mem_startb;
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| Line 801... |
Line 831... |
.mem_burst_wr (mem_burst_wr), // Start RX burst
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.mem_burst_wr (mem_burst_wr), // Start RX burst
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.mem_bw (mem_bw) // Burst byte width
|
.mem_bw (mem_bw) // Burst byte width
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);
|
);
|
|
|
`else
|
`else
|
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assign dbg_uart_txd = 1'b1;
|
|
`ifdef DBG_I2C
|
|
`else
|
assign dbg_addr = 6'h00;
|
assign dbg_addr = 6'h00;
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assign dbg_din = 16'h0000;
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assign dbg_din = 16'h0000;
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assign dbg_rd = 1'b0;
|
assign dbg_rd = 1'b0;
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assign dbg_uart_txd = 1'b0;
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assign dbg_wr = 1'b0;
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assign dbg_wr = 1'b0;
|
`endif
|
`endif
|
|
`endif
|
|
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//=============================================================================
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//=============================================================================
|
// 10) JTAG COMMUNICATION
|
// 10) I2C COMMUNICATION
|
//=============================================================================
|
//=============================================================================
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`ifdef DBG_JTAG
|
`ifdef DBG_I2C
|
JTAG INTERFACE IS NOT SUPPORTED YET
|
omsp_dbg_i2c dbg_i2c_0 (
|
|
|
|
// OUTPUTs
|
|
.dbg_addr (dbg_addr), // Debug register address
|
|
.dbg_din (dbg_din), // Debug register data input
|
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.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
|
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.dbg_rd (dbg_rd), // Debug register data read
|
|
.dbg_wr (dbg_wr), // Debug register data write
|
|
|
|
// INPUTs
|
|
.dbg_clk (dbg_clk), // Debug unit clock
|
|
.dbg_dout (dbg_dout), // Debug register data output
|
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.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
|
|
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
|
|
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
|
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.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
|
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.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
|
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.dbg_rst (dbg_rst), // Debug unit reset
|
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.mem_burst (mem_burst), // Burst on going
|
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.mem_burst_end (mem_burst_end), // End TX/RX burst
|
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.mem_burst_rd (mem_burst_rd), // Start TX burst
|
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.mem_burst_wr (mem_burst_wr), // Start RX burst
|
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.mem_bw (mem_bw) // Burst byte width
|
|
);
|
|
|
`else
|
`else
|
|
assign dbg_i2c_sda_out = 1'b1;
|
`endif
|
`endif
|
|
|
endmodule // dbg
|
endmodule // omsp_dbg
|
|
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_undefines.v"
|
`include "openMSP430_undefines.v"
|
`endif
|
`endif
|
