| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 154 $
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// $Rev: 175 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-10-15 22:44:20 +0200 (Mon, 15 Oct 2012) $
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// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Wed, 30 Jan 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 77... |
Line 77... |
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
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decode_noirq, // Frontend decode instruction
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decode_noirq, // Frontend decode instruction
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eu_mab, // Execution-Unit Memory address bus
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eu_mab, // Execution-Unit Memory address bus
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mdb_in, // Memory data bus input
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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fe_mdb_in, // Frontend Memory data bus input
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fe_mdb_in, // Frontend Memory data bus input
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pc, // Program counter
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pc, // Program counter
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puc_pnd_set // PUC pending set for the serial debug interface
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puc_pnd_set // PUC pending set for the serial debug interface
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);
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);
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|
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| Line 120... |
Line 116... |
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
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input decode_noirq; // Frontend decode instruction
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input decode_noirq; // Frontend decode instruction
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input eu_mb_en; // Execution-Unit Memory bus enable
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input eu_mb_en; // Execution-Unit Memory bus enable
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input puc_pnd_set; // PUC pending set for the serial debug interface
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input puc_pnd_set; // PUC pending set for the serial debug interface
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| Line 433... |
Line 425... |
wire mem_addr_wr = reg_wr[MEM_ADDR];
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wire mem_addr_wr = reg_wr[MEM_ADDR];
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wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
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wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
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wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
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wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
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|
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wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
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wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
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(dbg_mem_acc & ~mem_bw) ? 16'h0002 :
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(mem_burst & dbg_mem_acc & ~mem_bw) ? 16'h0002 :
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(dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
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(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
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|
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) mem_addr <= 16'h0000;
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if (dbg_rst) mem_addr <= 16'h0000;
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else if (mem_addr_wr) mem_addr <= dbg_din;
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else if (mem_addr_wr) mem_addr <= dbg_din;
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else mem_addr <= mem_addr + mem_addr_inc;
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else mem_addr <= mem_addr + mem_addr_inc;
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| Line 485... |
Line 477... |
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
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.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_din (dbg_din), // Debug register data input
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.dbg_din (dbg_din), // Debug register data input
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
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.exec_done (exec_done), // Execution completed
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
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.pc (pc) // Program counter
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.pc (pc) // Program counter
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);
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);
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|
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`else
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`else
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assign brk0_halt = 1'b0;
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assign brk0_halt = 1'b0;
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| Line 527... |
Line 516... |
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
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.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_din (dbg_din), // Debug register data input
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.dbg_din (dbg_din), // Debug register data input
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
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.exec_done (exec_done), // Execution completed
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
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.pc (pc) // Program counter
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.pc (pc) // Program counter
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);
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);
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|
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`else
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`else
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assign brk1_halt = 1'b0;
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assign brk1_halt = 1'b0;
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| Line 569... |
Line 555... |
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
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.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_din (dbg_din), // Debug register data input
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.dbg_din (dbg_din), // Debug register data input
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
|
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
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.exec_done (exec_done), // Execution completed
|
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
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.pc (pc) // Program counter
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.pc (pc) // Program counter
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);
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);
|
|
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`else
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`else
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assign brk2_halt = 1'b0;
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assign brk2_halt = 1'b0;
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| Line 611... |
Line 594... |
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
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.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
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.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_clk (dbg_clk), // Debug unit clock
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.dbg_din (dbg_din), // Debug register data input
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.dbg_din (dbg_din), // Debug register data input
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.dbg_rst (dbg_rst), // Debug unit reset
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.dbg_rst (dbg_rst), // Debug unit reset
|
|
.decode_noirq (decode_noirq), // Frontend decode instruction
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
|
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
|
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
|
|
.eu_mdb_out (eu_mdb_out), // Memory data bus output
|
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.exec_done (exec_done), // Execution completed
|
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.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
|
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.pc (pc) // Program counter
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.pc (pc) // Program counter
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);
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);
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|
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`else
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`else
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assign brk3_halt = 1'b0;
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assign brk3_halt = 1'b0;
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