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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 34 $
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// $Rev: 53 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2010-01-27 19:17:14 +0100 (Wed, 27 Jan 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module omsp_dbg (
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module omsp_dbg (
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// INPUTs
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// INPUTs
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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dbg_mem_din, // Debug unit Memory data input
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dbg_mem_din, // Debug unit Memory data input
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dbg_reg_din, // Debug unit CPU register data input
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dbg_reg_din, // Debug unit CPU register data input
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dbg_uart_rxd, // Debug interface: UART RXD
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dbg_uart_rxd, // Debug interface: UART RXD
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decode, // Frontend decode instruction
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decode_noirq, // Frontend decode instruction
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eu_mab, // Execution-Unit Memory address bus
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eu_mab, // Execution-Unit Memory address bus
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mdb_in, // Memory data bus input
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eu_mdb_in, // Memory data bus input
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eu_mdb_out, // Memory data bus output
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eu_mdb_out, // Memory data bus output
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//=========
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//=========
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input dbg_halt_st; // Halt/Run status from CPU
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input dbg_halt_st; // Halt/Run status from CPU
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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input dbg_uart_rxd; // Debug interface: UART RXD
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input dbg_uart_rxd; // Debug interface: UART RXD
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input decode; // Frontend decode instruction
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input decode_noirq; // Frontend decode instruction
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input eu_mb_en; // Execution-Unit Memory bus enable
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input eu_mb_en; // Execution-Unit Memory bus enable
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_out; // Memory data bus output
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input [15:0] eu_mdb_out; // Memory data bus output
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wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
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wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
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// Software break
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// Software break
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//--------------------------
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//--------------------------
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assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode & cpu_ctl[`SW_BRK_EN];
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assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
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// Single step
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// Single step
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//--------------------------
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//--------------------------
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reg [1:0] inc_step;
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reg [1:0] inc_step;
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