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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 34 $
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// $Rev: 57 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module omsp_dbg_hwbrk (
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module omsp_dbg_hwbrk (
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Line 131... |
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wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
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wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) brk_ctl <= 5'h00;
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if (por) brk_ctl <= 5'h00;
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else if (brk_ctl_wr) brk_ctl <= dbg_din[4:0];
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else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
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// BRK_STAT Register
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// BRK_STAT Register
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Line 144... |
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
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// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [5:0] brk_stat;
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reg [5:0] brk_stat;
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wire brk_stat_wr = brk_reg_wr[BRK_STAT];
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wire brk_stat_wr = brk_reg_wr[BRK_STAT];
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wire [5:0] brk_stat_set = {range_wr_set, range_rd_set,
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wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
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range_rd_set & `HWBRK_RANGE,
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addr1_wr_set, addr1_rd_set,
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addr1_wr_set, addr1_rd_set,
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addr0_wr_set, addr0_rd_set};
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addr0_wr_set, addr0_rd_set};
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wire [5:0] brk_stat_clr = ~dbg_din[5:0];
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wire [5:0] brk_stat_clr = ~dbg_din[5:0];
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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Line 207... |
// Note: here the comparison logic is instanciated several times in order
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// Note: here the comparison logic is instanciated several times in order
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// to improve the timings, at the cost of a bit more area.
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// to improve the timings, at the cost of a bit more area.
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & brk_ctl[`BRK_RANGE];
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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reg fe_mb_en_buf;
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reg fe_mb_en_buf;
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) fe_mb_en_buf <= 1'b0;
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if (por) fe_mb_en_buf <= 1'b0;
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else fe_mb_en_buf <= fe_mb_en;
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else fe_mb_en_buf <= fe_mb_en;
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & brk_ctl[`BRK_RANGE];
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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// Detect accesses
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// Detect accesses
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//---------------------------
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//---------------------------
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