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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_hwbrk.v] - Diff between revs 34 and 57

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Rev 34 Rev 57
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 34 $
// $Rev: 57 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 20:10:34 +0100 (Tue, 29 Dec 2009) $
// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  omsp_dbg_hwbrk (
module  omsp_dbg_hwbrk (
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wire        brk_ctl_wr = brk_reg_wr[BRK_CTL];
wire        brk_ctl_wr = brk_reg_wr[BRK_CTL];
 
 
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
  if (por)             brk_ctl <=  5'h00;
  if (por)             brk_ctl <=  5'h00;
  else if (brk_ctl_wr) brk_ctl <=  dbg_din[4:0];
  else if (brk_ctl_wr) brk_ctl <=  {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
 
 
wire  [7:0] brk_ctl_full = {3'b000, brk_ctl};
wire  [7:0] brk_ctl_full = {3'b000, brk_ctl};
 
 
 
 
// BRK_STAT Register
// BRK_STAT Register
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//    Reserved  RANGE_WR  RANGE_RD  ADDR1_WR  ADDR1_RD  ADDR0_WR  ADDR0_RD
//    Reserved  RANGE_WR  RANGE_RD  ADDR1_WR  ADDR1_RD  ADDR0_WR  ADDR0_RD
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
reg   [5:0] brk_stat;
reg   [5:0] brk_stat;
 
 
wire        brk_stat_wr  = brk_reg_wr[BRK_STAT];
wire        brk_stat_wr  = brk_reg_wr[BRK_STAT];
wire  [5:0] brk_stat_set = {range_wr_set, range_rd_set,
wire  [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
 
                            range_rd_set & `HWBRK_RANGE,
                            addr1_wr_set, addr1_rd_set,
                            addr1_wr_set, addr1_rd_set,
                            addr0_wr_set, addr0_rd_set};
                            addr0_wr_set, addr0_rd_set};
wire  [5:0] brk_stat_clr = ~dbg_din[5:0];
wire  [5:0] brk_stat_clr = ~dbg_din[5:0];
 
 
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
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// Note: here the comparison logic is instanciated several times in order
// Note: here the comparison logic is instanciated several times in order
//       to improve the timings, at the cost of a bit more area.
//       to improve the timings, at the cost of a bit more area.
 
 
wire        equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire        equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire        equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire        equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire        equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &  brk_ctl[`BRK_RANGE];
wire        equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
 
                          brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
 
 
reg         fe_mb_en_buf;
reg         fe_mb_en_buf;
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
  if (por)  fe_mb_en_buf <=  1'b0;
  if (por)  fe_mb_en_buf <=  1'b0;
  else      fe_mb_en_buf <=  fe_mb_en;
  else      fe_mb_en_buf <=  fe_mb_en;
 
 
wire        equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire        equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire        equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire        equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire        equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1))    &  brk_ctl[`BRK_RANGE];
wire        equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
 
                          brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
 
 
 
 
// Detect accesses
// Detect accesses
//---------------------------
//---------------------------
 
 

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