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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_uart.v] - Diff between revs 74 and 85

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 74 $
// $Rev: 85 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  omsp_dbg_uart (
module  omsp_dbg_uart (
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// Receive/Transmit buffer
// Receive/Transmit buffer
//-------------------------
//-------------------------
wire [19:0] xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
wire [19:0] xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
 
 
always @ (posedge mclk or posedge por)
always @ (posedge mclk or posedge por)
  if (por)               xfer_buf <=  18'h00000;
  if (por)               xfer_buf <=  20'h00000;
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
 
 
 
 
// Generate TXD output
// Generate TXD output

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