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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 86... |
Line 86... |
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//=============================================================================
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//=============================================================================
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// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
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// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
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//=============================================================================
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//=============================================================================
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// Synchronize RXD input & buffer
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// Synchronize RXD input
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//--------------------------------
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//--------------------------------
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reg [3:0] rxd_sync;
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`ifdef SYNC_DBG_UART_RXD
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wire uart_rxd_n;
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omsp_sync_cell sync_cell_uart_rxd (
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.data_out (uart_rxd_n),
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.clk (dbg_clk),
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.data_in (~dbg_uart_rxd),
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.rst (dbg_rst)
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);
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wire uart_rxd = ~uart_rxd_n;
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`else
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wire uart_rxd = dbg_uart_rxd;
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`endif
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// RXD input buffer
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//--------------------------------
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reg [1:0] rxd_buf;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) rxd_sync <= 4'hf;
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if (dbg_rst) rxd_buf <= 2'h3;
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else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
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else rxd_buf <= {rxd_buf[0], uart_rxd};
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// Majority decision
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// Majority decision
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//------------------------
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//------------------------
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reg rxd_maj;
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reg rxd_maj;
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wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
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wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd} +
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{1'b0, rxd_sync[2]} +
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{1'b0, rxd_buf[0]} +
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{1'b0, rxd_sync[3]};
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{1'b0, rxd_buf[1]};
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wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
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wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) rxd_maj <= 1'b0;
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if (dbg_rst) rxd_maj <= 1'b0;
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else rxd_maj <= rxd_maj_nxt;
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else rxd_maj <= rxd_maj_nxt;
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