| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 117 $
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// $Rev: 134 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-06-23 21:30:51 +0200 (Thu, 23 Jun 2011) $
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// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 99... |
Line 99... |
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wire uart_rxd_n;
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wire uart_rxd_n;
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omsp_sync_cell sync_cell_uart_rxd (
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omsp_sync_cell sync_cell_uart_rxd (
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.data_out (uart_rxd_n),
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.data_out (uart_rxd_n),
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.clk (dbg_clk),
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.data_in (~dbg_uart_rxd),
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.data_in (~dbg_uart_rxd),
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.clk (dbg_clk),
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.rst (dbg_rst)
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.rst (dbg_rst)
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);
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);
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wire uart_rxd = ~uart_rxd_n;
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wire uart_rxd = ~uart_rxd_n;
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`else
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`else
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wire uart_rxd = dbg_uart_rxd;
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wire uart_rxd = dbg_uart_rxd;
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| Line 119... |
Line 119... |
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// Majority decision
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// Majority decision
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//------------------------
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//------------------------
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reg rxd_maj;
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reg rxd_maj;
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wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd} +
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wire rxd_maj_nxt = (uart_rxd & rxd_buf[0]) |
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{1'b0, rxd_buf[0]} +
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(uart_rxd & rxd_buf[1]) |
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{1'b0, rxd_buf[1]};
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(rxd_buf[0] & rxd_buf[1]);
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wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) rxd_maj <= 1'b0;
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if (dbg_rst) rxd_maj <= 1'b1;
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else rxd_maj <= rxd_maj_nxt;
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else rxd_maj <= rxd_maj_nxt;
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wire rxd_s = rxd_maj;
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wire rxd_s = rxd_maj;
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wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
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wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
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wire rxd_re = ~rxd_maj & rxd_maj_nxt;
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wire rxd_re = ~rxd_maj & rxd_maj_nxt;
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wire rxd_edge = rxd_maj ^ rxd_maj_nxt;
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//=============================================================================
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//=============================================================================
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// 2) UART STATE MACHINE
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// 2) UART STATE MACHINE
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//=============================================================================
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//=============================================================================
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| Line 145... |
Line 144... |
reg [2:0] uart_state_nxt;
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reg [2:0] uart_state_nxt;
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wire sync_done;
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wire sync_done;
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wire xfer_done;
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wire xfer_done;
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reg [19:0] xfer_buf;
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reg [19:0] xfer_buf;
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wire [19:0] xfer_buf_nxt;
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// State machine definition
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// State machine definition
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parameter RX_SYNC = 3'h0;
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parameter RX_SYNC = 3'h0;
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parameter RX_CMD = 3'h1;
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parameter RX_CMD = 3'h1;
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parameter RX_DATA1 = 3'h2;
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parameter RX_DATA1 = 3'h2;
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parameter RX_DATA2 = 3'h3;
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parameter RX_DATA2 = 3'h3;
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parameter TX_DATA1 = 3'h4;
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parameter TX_DATA1 = 3'h4;
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parameter TX_DATA2 = 3'h5;
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parameter TX_DATA2 = 3'h5;
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// State transition
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// State transition
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always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
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always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
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case (uart_state)
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case (uart_state)
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RX_SYNC : uart_state_nxt = RX_CMD;
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RX_SYNC : uart_state_nxt = RX_CMD;
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RX_CMD : uart_state_nxt = mem_burst_wr ?
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RX_CMD : uart_state_nxt = mem_burst_wr ?
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(mem_bw ? RX_DATA2 : RX_DATA1) :
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(mem_bw ? RX_DATA2 : RX_DATA1) :
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mem_burst_rd ?
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mem_burst_rd ?
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(mem_bw ? TX_DATA2 : TX_DATA1) :
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(mem_bw ? TX_DATA2 : TX_DATA1) :
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(xfer_buf[`DBG_UART_WR] ?
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(xfer_buf_nxt[`DBG_UART_WR] ?
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(xfer_buf[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
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(xfer_buf_nxt[`DBG_UART_BW] ? RX_DATA2 : RX_DATA1) :
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(xfer_buf[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
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(xfer_buf_nxt[`DBG_UART_BW] ? TX_DATA2 : TX_DATA1));
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RX_DATA1 : uart_state_nxt = RX_DATA2;
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RX_DATA1 : uart_state_nxt = RX_DATA2;
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RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
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RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
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(mem_bw ? RX_DATA2 : RX_DATA1) :
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(mem_bw ? RX_DATA2 : RX_DATA1) :
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RX_CMD;
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RX_CMD;
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TX_DATA1 : uart_state_nxt = TX_DATA2;
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TX_DATA1 : uart_state_nxt = TX_DATA2;
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TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
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TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
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(mem_bw ? TX_DATA2 : TX_DATA1) :
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(mem_bw ? TX_DATA2 : TX_DATA1) :
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RX_CMD;
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RX_CMD;
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// pragma coverage off
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default : uart_state_nxt = RX_CMD;
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default : uart_state_nxt = RX_CMD;
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// pragma coverage on
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endcase
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endcase
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// State machine
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// State machine
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always @(posedge dbg_clk or posedge dbg_rst)
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always @(posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) uart_state <= RX_SYNC;
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if (dbg_rst) uart_state <= RX_SYNC;
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else if (xfer_done | sync_done |
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else if (xfer_done | sync_done |
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mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
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mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
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// Utility signals
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// Utility signals
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wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
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wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
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wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
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wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
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wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
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//=============================================================================
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//=============================================================================
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// 3) UART SYNCHRONIZATION
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// 3) UART SYNCHRONIZATION
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| Line 207... |
Line 210... |
`ifdef DBG_UART_AUTO_SYNC
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`ifdef DBG_UART_AUTO_SYNC
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reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
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reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
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if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
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else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
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else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
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`else
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`else
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
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`endif
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`endif
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| Line 227... |
Line 230... |
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
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reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
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assign xfer_done = (xfer_bit==4'hb);
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assign xfer_done = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) xfer_bit <= 4'h0;
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if (dbg_rst) xfer_bit <= 4'h0;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
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if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
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else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
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else if (rx_active & rxd_edge) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
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else if (|xfer_cnt) xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
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// Receive/Transmit buffer
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// Receive/Transmit buffer
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//-------------------------
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//-------------------------
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wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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assign xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) xfer_buf <= 20'h00000;
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if (dbg_rst) xfer_buf <= 20'h00000;
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else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
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else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
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else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
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else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
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| Line 268... |
Line 271... |
//=============================================================================
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//=============================================================================
|
|
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reg [5:0] dbg_addr;
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reg [5:0] dbg_addr;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) dbg_addr <= 6'h00;
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if (dbg_rst) dbg_addr <= 6'h00;
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else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
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else if (cmd_valid) dbg_addr <= xfer_buf_nxt[`DBG_UART_ADDR];
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|
|
reg dbg_bw;
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reg dbg_bw;
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) dbg_bw <= 1'b0;
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if (dbg_rst) dbg_bw <= 1'b0;
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else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
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else if (cmd_valid) dbg_bw <= xfer_buf_nxt[`DBG_UART_BW];
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|
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wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
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wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
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|
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wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
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wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf_nxt[18:11]} :
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{xfer_buf[18:11], xfer_buf[8:1]};
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{xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
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wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
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wire dbg_wr = (xfer_done & (uart_state==RX_DATA2));
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wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
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wire dbg_rd = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
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(cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
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(cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;
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|
|
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endmodule // omsp_dbg_uart
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endmodule // omsp_dbg_uart
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